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is25wp 128 is25wp 064 is25wp 032 128/64/ 32 m-bit 1.8v serial flash memory with 133mhz multi i/o spi & quad i/o qpi dtr interface advanced data sheet
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 2 rev. 00b 11/14/2014 features ? ind ustry standard serial interface - is25wp 128 : 128m -bit/16m -byte - is25wp 064: 64m -bit/8m -byte - is25wp 032: 32m -bit/4m -byte - 256 bytes per programmable page - supports standard spi, fast, dual, dual i/o, quad, quad i/o, spi dtr, dual i/o dtr, quad i/o dtr, and qpi - supports serial flash discoverable parameters (sfdp) ? high performance serial flash (spi) - 50mhz normal and 133mhz fast read - 532 mhz equivalent qpi - dtr (dual transfer rate) up to 66mhz - selectable dummy cycles - configurable drive strength - supports spi modes 0 and 3 - more than 100,000 erase/program cycles - more than 20-year data retention ? flexible & efficient memory architecture - chip erase with uniform: sector/bloc k era s e (4k/32k/64k-byte) - program 1 to 256 bytes per page - program/erase suspend & resume ? efficient read and program modes - low instruction overhead operations - continuous read 8/16/32/64-by te burst - selectable burst length - qpi for reduced instruction overhead - autoboot operation ? low power with wide temp. ranges - single 1.65v to 1.95v voltage supply - 10 ma active read current - 8 a standby current - 1 a deep power down - temp grades: extended: -40c to +105c v grade: -40c to +125c auto grade: up to +125c ? advanced security protection - software and hardware write protection - power supply lock protect - 4x256-byte dedicated security area with user-lockable bits, (otp) one time programmable memory - 128 bit unique id for each device ? indus try standard pin-out & packages (1) - jm = 16 -pin soic 300mil (2) - jb = 8-pin soic 208mil - jf = 8-pin vsop 208mil - jk = 8-contact wson 6x5mm - jl = 8-contact wson 8x6mm - jg= 24-ball tfbga 6x8 mm - kgd (call factory) notes: 1. call factory for other package options available 2. for the additional reset# pin option, call factory 128/64/ 32m - bit 1.8v serial flash memory with 133mhz multi i/ o spi & quad i/o qpi dtr int erface advanced information
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 3 rev. 00b 11/14/2014 general description the is25wp128/064/032 serial flash memory offers a versatile storage solution with high flexibility and performance in a simplified pin count package. issis industry standard serial interface f lash is for systems that require limited space, a low pin count, and low power consumption. the is25wp128/064/032 is accessed through a 4-wire spi interface consisting of a serial data input (sl), serial data output (so), serial clock (sck), and chip enable (ce#) pins, which can also be configured to serve as multi-i/o (see pin descriptions). the device supports dual and quad i/o as well as standard , dual output, and quad output spi. clock frequencies of up to 133mhz allow for equivalent clock rates of up to 532mhz (133mhz x 4) allowing more than 66mbytes/s of data th roughput. the is25xp series of flash adds support for dtr (double transfer rate) commands that transfer address es and read data on both edges of the clock. these transfer rates can outperform 16-bit parallel flash memories allowing for efficient memory access to support xip (execute in place) operatio n. the memory array is organized into programmable pages of 256-bytes. this family supports page program mode where 1 to 256 bytes of data are programmed in a single command. qpi (quad peripheral interface) supports 2-cycle instruction further reducing instruction times. pages can be erased in groups of 4k-byte sectors, 32k-byte blocks, 64k-byte blocks, and/ or the entire chip. the uniform sector and block architecture allows for a high degree of flexibility so that the device can be utilized for a broad va riety of applications requiring solid data retention. glossary standard spi in this operation, a 4-wire spi interface is utilized, consisting of serial data input (sl), serial data output (so), serial clock (sck), and chip enable (ce#) pins. instructions are sent via the si pin to encode instructions, addresses, or input data to the device on the rising edge of sck. the do pin is used to read data or to check the status of the device on the falling edge of sck. this device supports spi bus operation modes (0,0) and (1,1). mutil i/o spi multi-i/o operation utilizes an enhanced spi protocol to allow the device to function with dual output, dual in put and output, and quad input and output capability. executing these instructions through spi mode will achieve double or quadruple the transfer bandwidth for read and program operations. quad i/o q pi the is25wp128/064/032 enables qpi protocol by issuing an enter qpi mode (35h) command. the qpi mode uses four io pins for input and output to decrease spi instruction overhead and increase output bandwidth. si and so pins become bidirectional io0 and io1, and wp# and hold# pins become io2 and io3 respectively during qpi mode. issuing an exit qpi (f5h) command will cause the device to exit qpi m ode. power reset or hardware/software reset can also return the device into the standard spi mode. dtr in addition to spi and qpi features, the is25wp128/064/032 also supports spi dtr read. spi dtr allows high data throughput while running at lower clock frequencies. spi dtr read mode uses both rising and falling edges of the clock to drive output, resulting in reducing the dummy cycles by half. programmable drive strength and selectable burst setting the is25wp128/064/032 offers programmable output drive strength and selectable burst (wrap) length features to increase the efficiency and performance of read operation. the driver strength and burst setting features are controlled by setting the read registers. a total of six different drive strengths and four different burst sizes (8/16/32/64 bytes) are available for selection.
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 4 rev. 00b 11/14/2014 table of contents features .......................................................................................................................................................... 2 general description .................................................................................................................................. 3 1. pin configuration ................................................................................................................................ . 7 2. pin descriptions .................................................................................................................................... 8 3. block diagram ...................................................................................................................................... 10 4. spi modes description ...................................................................................................................... 11 5. system configuration ...................................................................................................................... 13 5.1 block/sector addresses .......................................................................................................... 13 6. registers ............................................................................................................................................... 14 6.1 status register ............................................................................................................................ 14 6.2 function register ........................................................................................................................ 17 6.3 read register and extended read register ..................................................................... 18 6.4 autoboot register ...................................................................................................................... 21 7. protection mode ................................................................................................................................ . 22 7.1 hardware write protection .................................................................................................... 22 7. 2 software write protection .................................................................................................... 22 8. device operation ................................................................................................................................ 23 8.1 normal read operation (nord, 03h) ....................................................................................... 26 8.2 fast read operation (frd, 0b h) ................................................................................................ 28 8.3 hold operation .............................................................................................................................. 30 8.4 fast read dual i/o operation (frdio, bbh) ........................................................................... 30 8.5 fast read dual output operation (frdo, 3bh) ................................................................... 33 8.6 fast read quad output operation (frqo, 6bh) .................................................................. 35 8.7 fast read quad i/o operation (frqio, ebh) .......................................................................... 37 8.8 page program operation (pp, 02h) .......................................................................................... 41 8.9 quad input page program operation (ppq, 32h/38h) ........................................................ 43 8.10 erase operation ......................................................................................................................... 44 8.11 sector erase operation (ser, d7h/20h) ............................................................................... 45 8.12 block erase operation (ber32k:52h, ber64k:d8h) ............................................................ 46 8.13 chip erase operation (cer, c7h/60h) ..................................................................................... 48 8.14 write enable operation (wren, 06h) .................................................................................... 49 8.15 write disable operation (wrdi, 04h) ..................................................................................... 50 8.16 read status register operation (rdsr, 05h) ................................................................... 51 8.17 write status register operation (wrsr, 01h) ................................................................ . 52 8.18 read function register operation (rdfr, 48h) ............................................................... 53 8.19 write function register operation (wrfr, 42h) ............................................................. 54
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 5 rev. 00b 11/14/2014 8.20 enter quad peripheral interface (qpi) mode operation (qioen,35h; qiodi,f5h) . 55 8.21 program/erase suspend & resume ...................................................................................... 56 8.22 deep power down (dp, b9 h ) ................................ ...................................................................... 58 8.23 release deep power down (rdpd, abh) ............................................................................... 59 8.24 set read parameters operation (srpnv: 65h , srpv: c0 h/63h) ...................................... 60 8.25 set extended read parameters operation (serpnv: 85h , serpv: 83h) .................... 62 8.26 read read parameters operation (rdrpnv, 61h) ............................................................ 62 8.27 read extended read parameters operation (rdrpnv, 81h) ....................................... 62 8.28 read product identification (rdid, abh) ............................................................................ 63 8.29 read product identification by jedec id operation (rdjdid, 9fh; rdjdidq, afh) 65 8.30 read device manufacturer and device id operation (rdmdid, 90h) ........................ 66 8.31 read unique id number (rduid, 4bh) ...................................................................................... 67 8.32 read sfdp operation (rdsfdp, 5ah) ...................................................................................... 68 8.33 no operation (nop, 00h) ............................................................................................................. 68 8.34 software reset (reset-enable (rsten, 66h) and reset (rst, 99h)) and hardware reset ........................................................................................................................................................ 69 8.35 security information row ................................ ...................................................................... 70 8.36 information row erase operation (irer, 64h) ................................................................ . 71 8.37 information row program operation (irp, 62h) ............................................................. 72 8.38 information row read operation (irrd, 68h) ................................................................... 73 8.39 fast read dtr mode operation (frdtr, 0dh) ..................................................................... 74 8.40 fast read dual io dtr mode operation (frddtr, bdh) .................................................. 77 8.41 fast read quad io dtr mode operation (frqdtr, edh) ................................................. 80 8.42 sector lock/unlock functions ............................................................................................ 84 8.43 autoboot ........................................................................................................................................ 86 9. electrical characteristics ........................................................................................................... 90 9.1 absolute maximum ratings (1) ................................................................................................... 90 9.2 operating range ........................................................................................................................... 90 9.3 dc characteristics ...................................................................................................................... 91 9.4 ac measurement conditions .................................................................................................... 92 9.5 ac characteristics ...................................................................................................................... 93 9.6 serial input/output timing ........................................................................................................ 95 9.7 power-up and power-down ...................................................................................................... 97 9.8 program/erase performance ................................................................................................ . 98 9.9 reliability characteristics ..................................................................................................... 98 10. package type information ......................................................................................................... 99 10.1 8-pin jedec 208mil broad small outline integrated circuit (soic) package (jb) .......................... 99 10.2 8-contact ultra-thin small outline no-lead (wson) package 6x5mm (jk) .................................. 100
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 6 rev. 00b 11/14/2014 10.3 8-contact ultra-thin small outline no-lead (wson) package 8x6mm (jl) .................................. 101 10.4 8-pin 208mil vsop package (jf) .................................................................................................... 102 10.5 16 -lead plastic small outline package (300 mils body width) (jm) .................................................. 103 10.6 24 -ball thin profile fine pitch bga 6x8mm (jg) ............................................................................. 104 11. ordering information - valid part numbers .............................................................................. 105
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 7 rev. 00b 11/14/2014 1. pin configuration notes: 1. according to the p7 bit setting in read register, either hold# (p7=0) or reset# (p7=1) pin can be selected. 2. for the dedicated parts that dont have the additional reset# pin on pin3, either hold# or reset# pin can be selected on pin1 by the p7 bit setting in read register when qe=0. for the dedicated parts with additional reset# pin on pin3 , only hold# pin is selected for pin1 regardless of the p7 bit of read register when qe=0. 3. the dedicated parts have additional reset# pin (pin3) on 16-pin soic 300mil package. for the parts, function register bit0 (reset# enable/disable) will be set to 0. the reset# pin is in dependent of the p7 bit of read register and qe bit of status register. the reset# pin has an internal pull-up resistor and may be left floating if not used. call factory for the reset# pin option. hold # or reset# (io3) vcc ce# gnd sck 1 2 3 4 7 6 5 so (io1) si (io0 ) 8 wp# (io2) 6 3 ce# vcc sck si (io0 ) 7 8 5 4 1 2 gnd wp# (io2) so (io1) hold # or reset# (io3) 8 - pin soic 208mil 8 - pin vsop 208mil 8 - contact wson 6x5mm 8 - contact w son 8 x 6 mm 12 10 11 9 13 15 14 5 7 6 8 4 2 3 1 6 1 vcc hold# (io3) hold# or reset# (io3) sck ce# wp# (io2) gnd nc nc nc nc nc si (io0) s o (io 1 ) nc nc reset# (1) (1) (1) (2) (3) a1 a2 a3 a4 b1 b2 b3 b4 c1 c2 c3 c4 d1 d2 d3 d4 e1 e2 e3 e4 f1 f2 f3 f4 nc nc nc nc nc sck gnd vcc nc ce # nc wp #( io 2) nc so (io 1) si (io 0) hold# or reset # (io 3) nc nc nc nc nc nc nc nc top view , balls facing down
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 8 rev. 00b 11/14/2014 2. pin descriptions for all other packages except 16-pin soic 300mil with additional reset# pin option symbol type description ce# input chip enable: the chip enable (ce#) pin enables and disables the devices operation. when ce# is high the device is deselected and output pins are in a high impedance state. when deselected the devices non - critical internal circuitry power down to allow minimal levels of power consum ption while in a standby state. when ce# is pulled low the device will be selected and brought out of standby mode. the device is considered active and instructions can be written to, data read, and written to the device. after power - up, ce# must transition from high to low before a ne w instruction will be accepted. keeping ce# in a high state deselects the device and switches it into its low power state. data will not be accepted when ce# is high. si (io0), so (io1) input/output serial data input, serial output, and ios (si, so, io0, and io1): this device supports standard spi, dual spi, and quad spi operation. standard spi instructions use the unidirectional si (serial input) pin to write instructions, addresses, or data to the device on the rising edge of the serial clock (sck). standard spi a lso uses the unidirectional so (serial output) to read data or status from the device on the falling edge of the serial clock (sck). in dual and quad spi mode, si and so become bidirectional io pins to write instructions, addresses or data to the device on the rising edge of the serial clock (sck) and read data or status from the device on the falling edge of sck. quad spi instructions use the wp# and hold# pin s as io2 and io3 respectively. wp# (io 2 ) input/output write protect/serial data io (io2): the wp# pin protects the status register from being written in conjunction with the srwd bit . when the srwd is set to 1 and the wp# is pulled low , the status register bit s (srwd, qe, bp3, bp2, bp1, bp0) are write - protected and vice - versa for wp# high. w hen the srwd is set to 0, the status register is not write - protected regardless of wp# state. when the qe bit is set to 1, the wp# pin (write protect) function is not available since this pin is used for io2. hold# or reset# (io 3 ) input/output hold# or reset#/serial data io (io3): when the qe bit of status register is set to 1, hold# pin or reset# is not available since it becomes io3 . when qe=0, the pin acts as hold# or reset# and either one can be selected by the p7 bit setting in read register. h old# will be selected if p7=0 (default) and reset# will be selected if p7=1 . the hold# pin allows the device to be paused while it is selected. it p auses serial communication by the master device without resetting the serial sequence. the hold# pin is acti ve low. when hold# is in a low state and ce# is low, the so pin will be at high impedance. device operation can resume when hold# pin is brought to a high state. reset# pin is a hardware reset signal. when reset# is driven high, the memory is in the normal operating mode. when reset# is driven low, the memory enters reset mode and output is high - z. if reset# is driven low while an internal write, program, or erase operation is in progress, data may be lost. sck input serial data clock: synchronized clock for input and output timing operations. vcc power power: device core power supply gnd ground ground: connect to ground when referenced to vcc nc unused nc: pins labeled nc stand for no connect and should be left unco nnec ted.
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 9 rev. 00b 11/14/2014 for 16 -pin soic 300mil package with additional reset# pin option - reset# pin will be added to another pin without sharing with hold# pin (call factory for the parts) symbol type description ce# input same as the description in previous page si (io0), so (io1) input/output same as the description in previous page wp# (io 2 ) input/output same as the description in previous page hold# (io 3 ) input/output hold#/serial data io (io3): when the qe bit of status register is set to 1 , hold# pin is not available since it becomes io3. when qe=0 the pin acts as hold# regardless of the p7 bit of read register . the hold# pin allows the device to be paused while it is selected. it p auses serial communication by the master device without resetting the serial sequence. the hold# pin is active low. when hold# is in a low state and ce# is low, the so pin will be at high impedance. device operation can resume when hold# pin is brought to a high state. reset# input/output reset: this pin is available only for d edicated parts (call factory). the reset# pin is a hardware reset signal. when reset# is driven high, the memory is in the normal operating mode. when reset# is driven low, the memory enters reset mode and output is high - z. if reset# is driven low while an internal write, program, or erase operation is in progress, data may be lost. sck input same as the description in previous page vcc power same as the description in previous page gnd ground same as the description in previous page nc unused same as the description in previous page
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 10 rev. 00b 11/14/2014 3. block diagram note1: in case of 16-pin soic package, reset# pin will be added to another pin without sharing with hold# pin for the dedicated parts. call factory for the additional reset# pin option. wp# (io 2 ) control logic high voltage generator i/o buffers and data latches 256 bytes page buffer y-decoder x-decoder serial peripheral interface status register address latch & counter memory array ce # sck wp # ( io 2) si ( io 0) so (io 1) hold# or reset# ( io 3)
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 11 rev. 00b 11/14/2014 4. spi modes description multiple is25wp128/064/032 devices can be connected on the spi serial bus and controlled by a spi master, i.e. microcontroller, as shown in figure 4.1 . the devices support either of two spi modes: mode 0 (0, 0) mode 3 (1, 1) the difference between these two modes is the clock polarity. when the spi master is in stand-by mode, the serial clock remains at 0 (sck = 0) for mode 0 and the clock remains at 1 (sck = 1) for mode 3. please refer to figure 4 .2 and figure 4 .3 for spi and qpi mode. in both modes, the input data is latched on the rising edge of serial clock (sck), and the output data is available from the falling edge of sck. figure 4.1 connection diagram among spi master and spi slaves (memory devices) note s: 1. in case of 16-pin soic package, reset# pin will be added to another pin without sharing with hold# pin for the dedicated parts. call factory for the additional reset# pin option. 2. si and so pins become bidirectional io0 and io1, and wp# and hold# pins become io2 and io3 respectively during qpi mode. spi interface with (0,0 ) or (1,1) spi master (i.e . microcontroller) spi memory device spi memory device spi memory device sck so si sck sdi sdo ce # wp # hold# or reset sck so si ce # wp # hold# or reset# sck so si ce # wp # cs 3 cs 2 cs 1 hold# or reset#
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 12 rev. 00b 11/14/2014 figure 4.2 spi mode support figure 4.3 qpi mode support sck so si mode 0 (0,0) mode 3 (1,1) msb msb sck 20 ce # sck 4 0 4 0 3-byte address 16 12 8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 3 mode 0 io 0 io 1 21 5 1 5 1 17 13 9 22 6 2 6 2 18 14 10 23 7 3 7 3 19 15 11 mode bits io 2 io 3 c4 c0 c1c5 c2c6 c3c7 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 5 6 7 0 1 2 3 ... ... ... ... data 1 data 2 data 3
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 13 rev. 00b 11/14/2014 5. system configuration the memory array of the is25wp128/064/032 is divided into uniform 4 kbyte sectors or uniform 32k/64 kbyte blocks (a block consists of eight/sixteen adjacent sectors respectively ). table 5. 1 illustrates the memory map of the device. the status register controls how the memory is mapped. 5.1 block/sector address es table 5. 1 block/sector addresses of is25wp128/064/032 memory density block no. (64kbyte) block no. (32kbyte) sector no. sector size (kbytes) address range 32mb 64mb 128mb block 0 block 0 sector 0 4 000000h C 000 f ffh : : : block 1 : : : sector 15 4 00f 0 00h - 00ffffh block 1 block 2 sector 16 4 010000h C 010 f ffh : : : block 3 : : : sector 31 4 01f 0 00h - 01ffffh block 2 block 4 sector 32 4 0 2 0000h C 0 2 0 f ffh : : : block 5 : : : sector 47 4 0 2 f 0 00h C 0 2 ffffh : : : : : block 63 block 126 : : : block 127 sector 1023 4 3ff 0 00h C 3fffffh : : : : : : : : : : : : : : : block 127 : : : : : : : block 255 : : : sector 2047 4 7ff 0 00h C 7fffffh : : : : : : : : : : block 254 block 508 sector 4064 4 fe 0000h C fe 0fffh : : : block 509 : : : sector 4079 4 fe f000h C fe ffffh block 255 block 510 sector 4080 4 f f 0 000h C ff0 fffh : : : block 511 : : : sector 4095 4 f ff 000h C ff ffffh
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 14 rev. 00b 11/14/2014 6. registers the is25wp128/064/032 has three sets of registers: status, function and read. 6.1 status register status register format and status register bit definitions are described in table 6.1 & table 6.2. table 6.1 status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 srwd qe bp3 bp2 bp1 bp0 wel wip d efault 0 0 0 0 0 0 0 0 table 6.2 status register bit definition bit name definition read /write type bit 0 wip write in progress bit: "0" indicates the device is ready (default) "1" indicates a write cycle is in progress and the device is busy r volatile bit 1 wel write enable latch: "0" indicates the device is not write enabled (default) "1" indicates the device is write enabled r/w volatile bit 2 bp0 b lock protection bit: (see table 6. 4 for details) "0" indicates the specific blocks are not write - protected (default) "1" indicates the specific blocks are write - protected r/w non - volatile bit 3 bp1 bit 4 bp2 bit 5 bp3 bit 6 qe quad enable bit: 0 indicates the quad output function disable (default) 1 indicates the quad output function enable r/w non - volatile bit 7 srwd status register write disable: (see table 7.1 for details) "0" indicates the status register is not write - protected (default) "1" indicates the status register is write - protected r/w non - volatile the bp0, bp1, bp2, bp3 , srwd, and qe are non -volatile memory cells that can be written by a write status register (wrsr) instruction. the default value of the bp2, bp1, bp0, and srwd bits were set to 0 at factory. the status register can be read by the read status register (rdsr). the function of status register bits are described as follows: wip bit : the write in progress (wip) bit is read-only, and can be used to detect the progress or completion of a program or erase operation. when the wip bit is 0, the device is ready for write status register, program or erase operation. when the wip bit is 1, the device is busy. wel bit : the write enable latch (wel) bit indicates the status of the internal write enable latch. when the wel is 0, the write enable latch is disabled and the write operations described in table 6.3 are inhibited. when the wel bit is 1, the write operations are allowed. the wel bit is set by a write enable (wren) instruction. each write register, program and erase instruction except for set volatile read register and set volatile extended read register must be preceded by a wren instruction. the wel bit can be reset by a write disable (wrdi) instruction. it will automatically reset after the completion of any write operation.
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 15 rev. 00b 11/14/2014 table 6.3 instructions requiring wren instruction ahead instruction s must be preceded by the wren instruction name hex code operation pp 02h input page program ppq 32h/38h quad input page program ser d7h/20h sector erase ber32 (32kb) 52h block erase 32k ber64 (64kb) d8h block erase 64k cer c7h/60h chip erase wrsr 01h write status register wrfr 42h write function register srpnv 65h set read parameters (non - volatile) serpnv 85h set extended read parameters (non - volatile) irp 62h program information row wrabr e5h write autoboot register bp3, bp2, bp1, bp0 bits : the block protection (bp3, bp2, bp1 and bp0) bits are used to define the portion of the memory area to be protected. refer to table 6. 4 for the block write protection (bp) bit settings. when a defined combination of bp3, bp2, bp1 and bp0 bits are set, the corresponding memory area is protected. bp0~3 area assignment changed from top or bottom according to the tbs bit setting in function register. any program or erase operation to that area will be inhibited. note: a chip erase (cer) instruction will be ignored unless all the block protection bits are 0s. srwd bit : the status register write disable (srwd) bit operates in conjunction with the write protection :3vljqdowrsurylghd+dugzduh3urwhfwlrq0rgh:khqwkh65:'lvvhwwr3wkh6wdwxv5hjlvwhulvqrw write- surwhfwhg :khq wkh 65:' lv vhw wr 3 dqg wkh :3 lv sxoohg orz 9 il ), the bits of status register (srwd, qe, bp3, bp2, bp1, bp0) become read-only, and a wrsr instruction will be ignored. if the srwd is vhwwr3dqg:3lvsxoohgkljk9 ih ), the status register can be changed by a wrsr instruction. qe bit : the quad enable (qe) is a non-volatile bit in t he status register that allows quad operation. when the qe bit is set to 3 0 , the pin wp# and hold#/reset# are enabled. when the qe bit is set to 3 1 , the io2 and io3 pins are enabled. warning: the qe bit must be set to 0 if wp# or hold#/reset# pin is tied directly to the power supply.
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 16 rev. 00b 11/14/2014 table 6.4 block (64kbyte) assignment by block write protect (bp) bits status register bits protected memory area ( is25wp 128, 256blocks) bp3 bp2 bp1 bp0 tbs(t/b selection) = 0, top area tbs(t/b selection) = 1, bottom area 0 0 0 0 0( none) 0( none) 0 0 0 1 1(1 block : 255th) 1(1 block : 0th) 0 0 1 0 2(2 block s : 254th and 255th) 2(2 block s : 0th and 1st) 0 0 1 1 3(4 blocks : 252nd to 255th) 3(4 blocks : 0th to 3rd) 0 1 0 0 4(8 blocks : 248th to 255th) 4(8 blocks : 0th to 7th) 0 1 0 1 5(16 blocks :2 40th to 255th) 5(16 blocks : 0th to 15th) 0 1 1 0 6(32 blocks : 22 4th to 255th) 6(32 blocks : 0th to 31st) 0 1 1 1 7(64 blocks : 19 2nd to 255th) 7(64 blocks : 0th to 63rd) 1 0 0 0 8(128 blocks : 12 8 th to 255th) 8(128 blocks : 0th to 127th) 1 0 0 1 9(256 blocks : 0th to 255th) all blocks 9(256 blocks : 0th to 255th) all blocks 1 0 1 x 10 - 11(256 blocks : 0th to 255th) all blocks 10 - 11(256 blocks : 0th to 255th) all blocks 1 1 x x 12 - 15(256 blocks : 0th to 255th) all blocks 12 - 15(256 blocks : 0th to 255th) all blocks status register bits protected memory area( is25wp 064, 128blocks) bp3 bp2 bp1 bp0 tbs(t/b selection) = 0, top area tbs(t/b selection) = 1, bottom area 0 0 0 0 0( none) 0( none) 0 0 0 1 1(1 block : 127th) 1(1 block : 0th) 0 0 1 0 2(2 block s : 126th and 127th) 2(2 block s : 0th and 1st) 0 0 1 1 3(4 blocks : 124th to 127th) 3(4 blocks : 0th to 3rd) 0 1 0 0 4(8 blocks : 120th to 127th) 4(8 blocks : 0th to 7th) 0 1 0 1 5(16 blocks :112nd to 127th) 5(16 blocks : 0th to 15th) 0 1 1 0 6(32 blocks : 96th to 127th) 6(32 blocks : 0th to 31st) 0 1 1 1 7(64 blocks : 64th to 127th) 7(64 blocks : 0th to 63rd) 1 x x x 8~15(128 blocks : 0th to 127th) all blocks 8~15(128 blocks : 0th to 127th) all blocks status register bits protected memory area( is25wp 032, 64blocks) bp3 bp2 bp1 bp0 tbs(t/b selection) = 0, top area tbs(t/b selection) = 1, bottom area 0 0 0 0 0( none) 0( none) 0 0 0 1 1(1 block : 63rd) 1(1 block : 0th) 0 0 1 0 2(2 block s : 62nd and 63rd) 2(2 block s : 0th and 1st) 0 0 1 1 3(4 blocks : 60th to 63rd) 3(4 blocks : 0th to 3rd) 0 1 0 0 4(8 blocks : 56th to 63rd) 4(8 blocks : 0th to 7th) 0 1 0 1 5(16 blocks :4 8th to 63rd) 5(16 blocks : 0th to 15th) 0 1 1 0 6(32 blocks : 32nd to 63rd) 6(32 blocks : 0th to 31st) 0 1 1 1 7(64 blocks : 0th to 63rd) all blocks 7(64 blocks : 0th to 63rd) all blocks 1 x x x 8~15(64 blocks : 0th to 63rd) all blocks 8~15(64 blocks : 0th to 63rd) all blocks note : x is dont care
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 17 rev. 00b 11/14/2014 6.2 function register function register format and bit definition are described in table 6.5 and table 6. 6 table 6.5 function register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 irl3 irl2 irl1 irl0 esus psus tbs reset# enable/disable default 0 0 0 0 0 0 0 0 or 1 table 6.6 function register bit definition bit name definition read /write type bit 0 reset# enable/disable reset# enable/disable 0 indicates enable additional reset# 1 indicates disable additional reset# r/w for 0 r for 1 non - volatile bit 1 top/bottom selection top/bottom selection. ( see table 6. 4 for details ) 0 indicates top area 1 indicates bottom area r/w non - volatile bit 2 psus program suspend bit: 0 indicates program is not suspend 1 indicates program is suspend r volatile bit 3 esus erase suspend bit : "0" indicates erase is not suspend "1" indicates erase is suspend r volatile bit 4 ir lock 0 lock the information row 0: 0 indicates the information row can be programmed 1 indicates the information row cannot be programmed r/w non - volatile bit 5 ir lock 1 lock the information row 1: 0 indicates the information row can be programmed 1 indicates the information row cannot be programmed r/w non - volatile bit 6 ir lock 2 lock the information row 2: 0 indicates the information row can be programmed 1 indicates the information row cannot be programmed r/w non - volatile bit 7 ir lock 3 lock the information row 3: 0 indicates the information row can be programmed 1 indicates the information row cannot be programmed r/w non - volatile note: function register bits are only one time programmable and cannot be modified reset# enable/disable : the default of the bit is dependent on parts. the dedicated part that has additional reset# on pin3 for 16 -pin soic 300mil package will default to 0 for enabling additional reset# pin. all other parts will default to 1 for disabling additional reset# pin. if the bit defaults to 1 , it can t be programmed. top/bottom selection : bp0~3 area assignment changed from top or bottom. see table 6. 4 for details the program suspend status bit indicates when a program operation has been suspended. the psus changes to 1 after a suspend command is issued during the program operation. once the suspended program resumes, the psus bit is reset to 0 . esus bit : the erase suspend status indicates when an erase operation has been suspended. t he esus bit is 1 after a suspend command is issued during an erase operation. once the suspended erase resumes, the esus bit is reset to 0 . ir lock bit 0 ~ 3 : the information row lock bits are programmable. if the bit set to 1 , it can t be programmed.
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 18 rev. 00b 11/14/2014 6.3 read register and extended read register read register format and bit definitions are described below. read register and extended read register are rewritable non-volatile. it consists of a pair of non-volatile register and volatile register respectively. during power up sequence, volatile register will be loaded with the value of non-volatile value. read parameter bits table 6. 7 and table 6.8 define all bits that control features in spi/qpi modes. hold#/reset# pin selection (p7) bit is used to select hold# pin or reset# pin. for 16-pin soic, reset# pin will be a separate pin (pin3). the dummy cycle bits (p6, p5, p4, p3) define how many dummy cycles are used during various read modes. the wrap selection bits (p2, p1, p0) define burst length with an enable bit. the set read parameters operation (srpnv: 65 h, srpv: c0h or 63h ) is used to set all the read register bits, and can thereby define hold#/reset# pin selection, dummy cycles, and burst length with wrap around. srpnv is used to set the non-volatile register and srpv is used to set the volatile register. table 6.7 read register parameter bit table p7 p6 p5 p4 p3 p2 p1 p0 hold# / reset# dummy cycles dummy cycles dummy cycles dummy cycles wrap enable burst length burst length d efault 0 0 0 0 0 0 0 0 table 6.8 read register bit definition bit name definition read - /write type p0 burst length burst length r/w non - volatile and volatile p1 burst length burst length r/w non - volatile and volatile p2 burst length set enable burst length set enable bit: "0" indicates disable (default) "1" indicates enable r/w non - volatile and volatile p3 dummy cycles number of dummy cycles: bits1 to bit4 can be toggled to select the number of dummy cycles (1 to 15 cycles) r/w non - volatile and volatile p4 dummy cycles r/w non - volatile and volatile p5 dummy cycles r/w non - volatile and volatile p6 dummy cycles r/w non - volatile and volatile p7 hold#/ reset# hold#/reset# pin selection bit: "0" indicates the hold# pin is selected (default) "1" indicates the reset# pin is selected r/w non - volatile and volatile table 6.9 burst length data p1 p0 8 bytes 0 0 16 bytes 0 1 32 bytes 1 0 64 bytes 1 1
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 19 rev. 00b 11/14/2014 table 6.10 wrap function wrap around boundary p2 whole cell regardless of p1 and p0 value 0 burst length set by p1 and p0 1 table 6.11 read dummy cycles eb[4:1] dummy cycles 2,3 fast read 0bh fast read 0bh fast read dual output 3bh dual io read bbh fast read quad output 6bh quad io read ebh dtr spi qpi spi spi spi spi, qpi spi, qpi 4 0 default 1 133 mhz 104mhz 133mhz 104mhz 133mhz 104mhz 1 1 50mhz 50mhz 50mhz 50mhz 50mhz 50mhz 2 2 3 3 4 4 104mhz 84mhz 104mhz 104mhz 104mhz 84mhz 66mhz 5 5 66mhz 6 6 104mhz 104mhz 66mhz 7 7 66mhz 8 8 133mhz 133mhz 133mhz 133mhz 133mhz 133mhz 66mhz 9 9 133mhz 133mhz 133mhz 133mhz 133mhz 133mhz 66mhz 10 10 133mhz 133mhz 133mhz 133mhz 133mhz 133mhz 66mhz 11 11 133mhz 133mhz 133mhz 133mhz 133mhz 133mhz 66mhz 12 12 133mhz 133mhz 133mhz 133mhz 133mhz 133mhz 66mhz 13 13 133mhz 133mhz 133mhz 133mhz 133mhz 133mhz 66mhz 14 14 133mhz 133mhz 133mhz 133mhz 133mhz 133mhz 66mhz 15 15 133mhz 133mhz 133mhz 133mhz 133mhz 133mhz 66mhz notes: 1. default value is 0. in case of the default value, dummy cycles will be as follows. (not fixed number) operation command dummy cycles normal mode dtr mode normal mode dtr mode fast read spi 0bh 0dh 8 8 fast read qpi 0bh 0dh 6 6 fast read dual output 3bh - 8 - dual io read spi bbh bdh 4 4 fast read quad output 6bh - 8 - quad io read spi/qpi ebh edh 6 6 2. enough number of dummy cycles must be applied to execute properly the ax read operation. 3. must satisfy bus i/o contention. for instance, if the number of dummy cycles and ax bits cycles are same, then x must be hi- z. 4. qpi is not available for frddtr command
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 20 rev. 00b 11/14/2014 extended read parameter bits table 6.12 and table 6.13 define all bits that control features in spi/qpi modes. the ods2, ods1, ods0 ( eb7, eb6, eb 5) bits provide a method to set and control driver strength. the five bits (eb4, eb3, eb2, eb1, eb0) remain reserved for future use. the set extended read parameters operation (serpnv: 85h, serpv: 83h) is used to set all the extended read register bits, and can thereby define the output driver strength used during read modes. srpnv is used to set the non-volatile register and srpv is used to set the volatile register. table 6.12 extended read register bit table eb 7 eb 6 eb 5 eb 4 eb 3 eb 2 eb 1 eb 0 ods2 ods1 ods0 reserved reserved reserved reserved reserved d efault 1 1 1 1 1 1 1 1 table 6.13 extended read register bit definition bit name definition read - /write type eb0 reserved reserved r/w non - volatile and volatile eb1 reserved reserved r/w non - volatile and volatile eb2 reserved reserved r/w non - volatile and volatile eb 3 reserved reserved r/w non - volatile and volatile eb 4 reserved reserved r/w non - volatile and volatile eb 5 ods0 output driver strength: output drive strengt h can be selected according to t able 6.1 4 r/w non - volatile and volatile eb 6 ods1 r/w non - volatile and volatile eb 7 ods2 r/w non - volatile and volatile table 6.14 driver strength table ods2 ods1 ods0 description remark 0 0 0 reserved 0 0 1 12.50% 0 1 0 25% 0 1 1 37.50% 1 0 0 reserved 1 0 1 75% 1 1 0 100% 1 1 1 50% default
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 21 rev. 00b 11/14/2014 6.4 autoboot register autoboot register bit ( 32 bits) definitions are described in table 6.15. table 6.15 autoboot register parameter bit table bits symbols function type default value description ab[31:24] absa reserved [0h] non - volatile 00 00 000h reserved for future use ab[23:5] absa autoboot start address non - volatile 00000h 512 byte boundary address for the start of boot code access ab[4:1] absd autoboot start delay non - volatile 00h number of initial delay cycles between cs# going low and the first bit of boot code being transferred ab0 abe autoboot enable non - volatile 0 1 = autoboot is enabled 0 = autoboot is not enabled
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 22 rev. 00b 11/14/2014 7. protection mode the is25wp128/064/032 supports hardware and software write-protection mechanisms. 7.1 hardware write protection the write protection (wp#) pin provides a hardware write protection method for bp3, bp2, bp1, bp0, srwd, and qe in the status register. refer to the section 6.1 status register. write inhibit voltage (v wi ) is specified in the section 9.7 power-up and power-down . a ll write sequence will be ignored when vcc drops to v wi . table 7.1 hardware write protection on status register srwd wp# status register 0 low writable 1 low protected 0 high writable 1 high writable note: before the execution of any program, erase or write status register instruction, the write enable latch (wel) bit must be enabled by executing a write enable (wren) instruction. if the wel bit is not enabled, the program, erase or write register instruction will be ignored. 7.2 software write protection the is25wp128/064/032 also provides a software write protection feature . the block protection (tbs, bp3, bp2, bp1, bp0) bits allow part or the whole memory area to be write-protected.
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 23 rev. 00b 11/14/2014 8. device operation the is25wp128/064/032 utilizes an 8-bit instruction register. refer to table 8.1. instruction set for details on instructions and instruction codes. all instructions, addresses, and data are shifted in with the most significant bit (msb) first on serial data input (si) or serial data ios (io0, io1, io2, io3). the input data on si or ios is latched on the rising edge of serial clock (sck) for normal mode and both of rising and falling edges for dtr mode after chip enable (ce#) is driven low (v il ). every instruction sequence starts with a one-byte instruction code and is followed by address bytes, data bytes, or both address bytes and data bytes, depending on the type of instruction. ce# must be driven high (v ih ) after the last bit of the instruction sequence has been shifted in to end the operation. table 8.1 instruction set instruction name operation total bytes mode byte0 byte1 byte2 byte3 byte4 byte5 byte6 nord normal read mode 4 spi 03h a <23:16> a <15:8> a <7:0> data out frd fast read mode 5 spi qpi 0bh a <23:16> a <15:8> a <7:0> dummy (1) byte data out frdio fast read dual i/o 3 spi bbh a <23:16> dual a <15:8> dual a <7:0> dual axh (1),(2) dual dual data out frdo fast read dual output 5 spi 3bh a <23:16> a <15:8> a <7:0> dummy (1) byte dual data out frqio fast read quad i/o 2 spi qpi ebh a <23:16> quad a <15:8> quad a <7:0> quad axh (1), (2) quad quad data out frqo fast read quad output 5 spi 6bh a <23:16> a <15:8> a <7:0> dummy (1) byte quad data out frdtr fast read dtr mode 5 spi qpi 0dh a <23:16> a <15:8> a <7:0> dummy (1) byte dual data out frddtr fast read dual i/o dtr 3 spi bdh a <23:16> dual a <15:8> dual a <7:0> dual axh (1), (2) dual dual data out frqdtr fast read quad i/o dtr 5 spi qpi edh a <23:16> a <15:8> a <7:0> axh (1), (2) quad quad data out pp input page program 4 + 256 spi qpi 02h a <23:16> a <15:8> a <7:0> pd (256byte) ppq quad input page program 4 + 256 spi 32h 38h a <23:16> a <15:8> a <7:0> quad pd (256byte) ser sector erase 4 spi qpi d7h 20h a < 23:16> a <15:8> a <7:0> ber32 (32kb) block erase 32k 4 spi qpi 52h a <23:16> a <15:8> a <7:0> ber64 (64kb) block erase 64k 4 spi qpi d8h a <23:16> a <15:8> a <7:0> cer chip erase 1 spi qpi c7h 60h wren write enable 1 spi qpi 06h wrdi write disable 1 spi qpi 04h rdsr read status register 1 spi qpi 05h sr wrsr write statu s register 2 spi qpi 01h wsr data
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 24 rev. 00b 11/14/2014 instruction name operation total bytes mode byte0 byte1 byte2 byte3 byte4 byte5 byte6 rdfr read function register 1 spi qpi 48h data out wrfr write function register 2 spi qpi 42h wfr data qioen enter qpi mode 1 spi 35h qiodi exit qpi mode 1 qpi f5h persus suspend during program/erase 1 spi qpi 75h b0h perrsm resume program/erase 1 spi qpi 7ah 30h dp deep power down 1 spi qpi b9h rdid, rdpd read id / release power down 4 spi qpi abh xxh (3) xxh (3) xxh (3) id7 - id0 srpnv set read parameters (non - volatile) 2 spi qpi 65h data in srpv set read parameters (volatile) 2 spi qpi c0h 63h data in serpnv set extended read parameters (non - volatile) 2 spi qpi 85h data in serpv set extended read parameters (volatile) 2 spi qpi 83h data in rdrpnv read read parameters (non - volatile) 2 spi qpi 61h data out rderpnv read extended read parameters (non - volatile) 2 spi qpi 81h data out rdjdid read jedec id command 1 spi 9fh mf7 - mf0 id15 - id8 id7 - id0 rdmdid read manufacturer & device id 4 spi qpi 90h xxh (3) xxh (3) 00h mf7 - mf0 id7 - id0 01h id7 - id0 mf7 - mf0 rdjdidq read jedec id qpi mode 1 qpi afh mf7 - mf0 id15 - id8 id7 - id0 rduid read unique id 5 spi qpi 4bh a (4) <23:16> a (4) <15:8> a (4) <7:0> dummy byte data out rdsfdp sfdp read 5 spi qpi 5ah a <23:16> a <15:8> a <7:0> dummy byte data out nop no operation 1 spi qpi 00 h rsten software reset enable 1 spi qpi 66h rst software reset 1 spi qpi 99h
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 25 rev. 00b 11/14/2014 instruction name operation total bytes mode byte0 byte1 byte2 byte3 byte4 byte5 byte6 irer erase information row 4 spi qpi 64h a <23:16> a <15:8> a <7:0> irp program information row 4 + 256 spi qpi 62h a <23:16> a <15:8> a <7:0> pd (256byte) irrd read information row 5 spi qpi 68h a <23:16> a <15:8> a <7:0> dummy byte data out secun - lock sector unlock 4 spi qpi 26h a <23:16> a <15:8> a <7:0> seclock sector lock 1 spi qpi 24h rdabr read autoboot register 1 spi qpi e1h wrabr write autoboot register 5 spi qpi e5h data in 1 data in 2 data in 3 data in 4 notes: 1. the number of dummy cycles depends on the value setting in the table 6.11 read dummy cycles. 2. axh has to be counted as a part of dummy cycles. x means dont care. 3. xx means dont care. 4. a<23:9> are dont care and a<8:4> are always 0.
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 26 rev. 00b 11/14/2014 8.1 normal read operatio n (no rd, 03h) the normal read (nord) instruction is used to read memory contents of the is25wp128/064/032 at a maximum frequency of 50 mhz. the nord instruction code is transmitted via the si line, followed by three address bytes (a23 - a0) of the first memory location to be read. a total of 24 address bits are shifted in. the first byte address ed can be at any memory location. upon completion, any data on the si will be ignored. refer to table 8.2 for the related address key. the first byte data (d7 - d0) is shifted out on the so line, msb first. a single byte of data, or up to the whole memory array, can be read out in one normal re ad instruction. the address is automatically incremented by one after each byte of data is shifted out. the read operation can be terminated at any time by driving ce# high (vih) after the data comes out. when the highest address of the device is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read in one continuous read instruction. if the normal read instruction is issued while an erase, program or write operation is in process (wip=1) the instruction is ignored and will not have any effects on the current operation . table 8.2 address key address is25wp128 is25wp064 IS25WP032 a n ( a ms b C a 0) a 23 - a0 a 23 - a0 (a23=x) a 23 - a0 (a23 - a22=x) ; 'rq?w&duh
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 27 rev. 00b 11/14/2014 figure 8.1 normal read sequence 7 6 ce # sck si 5 3 2 so 4 1 0 data out 1 instruction = 03h 23 ce # sck si 3 2 so 1 0 3-byte address high impedance 22 21 ... 0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 mode 3 mode 0 48 7 6 5 3 2 4 1 0 t v data out 2
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 28 rev. 00b 11/14/2014 8.2 fast read operation (frd, 0b h) the fast read (frd) instruction is used to read memory data at up to a 1 33 mhz clock. the fast read instruction code is followed by three address bytes (a23 - a0) and a dummy byte (configurable, 8 clocks for 133mhz), transmitted via the si line, with each bit latched-in during the rising edge of sck. then the first data byte from the address is shifted out on the so line, with each bit shifted out at a maximum frequency f ct , during the falling edge of sck. the first byte addressed can be at any memory location. the address is automatically incremented by one after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single fast read instruction. the fast read instruction is terminated by driving ce# high (vih). if the fast read instruction is issued while an erase, program or write cycle is in process (wip=1) the instruction is ignored without affecting the current cycle. figure 8.2 fast read sequence 7 6 ce # sck si 5 3 2 so 4 1 0 data out instruction = 0bh 23 ce # sck si 3 2 so 1 0 3-byte address high impedance 22 21 ... 0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 mode 3 mode 0 48 ... t v dummy byte
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 29 rev. 00b 11/14/2014 fast read qpi operation ( fr d qpi, 0bh) the fast read qpi (frd qpi) instruction is used to read memory data at up to a 1 33 mhz clock. the fast read qpi instruction code (2 clocks) is followed by three address bytes (a23- a0 6 clocks) and dummy cycles (configurable, 6 cycles for 1 04 mhz), transmitted via the io3, io2, io1 and io0 lines, with each bit latched-in during the rising edge of sck. then the first data byte addressed is shifted out on the io3, io2, io1 and io0 lines, with each bit shifted out at a maximum frequency f ct , during the falling edge of sck. the first byte addressed can be at any memory location. the address is automatically incremented by one after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single fast read qpi instruction. the fast read qpi instruction is terminated by driving ce# high (vih). if the fast read qpi instruction is issued while an erase, program or write cycle is in process (wip=1) the instruction is ignored without affecting the current cycle. figure 8.3 fast read sequence, qpi mode note: number of dummy cycles depends on read parameter setting. detailed information in table 6.11 read dummy cycles. 0 bh ce # sck io [3:0] 6 dummy cycles address 0 1 2 3 4 5 6 7 8 9 ... 13 14 15 16 17 mode 3 mode 0 23 : 20 7:4 3:0 7:4 3:0 data 1 data 2 19 : 16 15 : 12 11 :8 7:4 3:0 18 t v ... instruction
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 30 rev. 00b 11/14/2014 8.3 hold operation hold# is used in conjunction with ce# to select the is25wp128/064/032. when the device is selected and a serial sequence is underway, hold# can be used to pause the serial communication with the master device without resetting the serial sequence. to pause, hold# is brought low while the sck signal is low. to resume serial communication, hold# is brought high while the sck signal is low (sck may still toggle during hold). inputs to slo will be ignored while so is in the high impedance state. note: hold is not supported in dtr mode or with qe=1 or when reset# is selected for the hold# or reset# pin. timing graph can be referenced in ac parameters figure 9.4 8.4 fast read dual i/o operation (frdio, bb h) the frdio allows the address bits to be input two bits at a time. this may allow for code to be executed directly from the spi in some applications. the frdio instruction code is followed by three address bytes (a23 C a0) and dummy cycles, transmitted via the io 1 and io0 lines, with each pair of bits latched-in during the rising edge of sck. the address msb is input on io1, the next bit on io0, and this shift pattern continues to alternate between the two lines. depending on the usage of ax read operation mode, a mode byte may be located after address input. the first data byte addressed is shifted out on the io1 and io0 lines, with each pair of bits shifted out at a maximum frequency f ct , during the falling edge of sck. the msb is output on io1, while simultaneously the second bit is output on io0. figure 8.4 illustrates the timing sequence. the first byte addressed can be at any memory location. the address is automatically incremented by one after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single frdio instruction. frdio instruction is terminated by driving ce# high (v ih ). the device supports the ax read operation by applying mode bits during dummy period. mode bits consist of 8 bits, such as m7 to m0. four cycles after address input are reserved for mode bits in frdio execution . m7 to m4 are important for enabling this mode. m3 to m0 become dont care for future use. when m[7:4]=1010(ah), it enables the ax read operation and subsequent frdio execution skips command code. it saves cycles as described in figure 8. 5. when the code is different from a xh (x is dont care), the device exits the ax read operation. after finishing the read operation, device becomes ready to receive a new command. spi or qpi mode configuration retains the prior setting. mode bit must be applied during dummy cycles. number of dummy cycles in table 6.11 includes number of mode bit cycles. if dummy cycles are configured as 4 cycles, data output will start right after mode bit is applied. if the frdio instruction is issued while an erase, program or write cycle is in process (wip=1) the instruction is ignored and will not affect the current cycle.
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 31 rev. 00b 11/14/2014 figure 8.4 fast read dual i/o sequence (with command decode cycles) notes: 1. if the mode bits=axh ( x: dont care), it can execute the ax read mode (without command). when the mode bits are different from axh (x is dont care), the device exits the ax read operation. 2. number of dummy cycles depends on clock speed. detailed information in table 6.11 read dummy cycles. 3. sufficient dummy cycles are required to avoid i/o contention. if the number of dummy cycles and ax bits cycles are same, then x should be hi- z. 7 5 3 7 5 1 3 1 data out 1 instruction = 03 h 22 ce # sck 2 0 6 4 3-byte address high impedance 20 18 ... 0 1 2 3 4 5 6 7 8 9 10 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 mode 3 mode 0 38 t v 23 3 1 7 5 21 19 ... io 0 io 1 3 1 2 0 6 4 2 6 4 0 2 0 4 dummy cycles 7 5 3 1 6 4 2 0 ... ... ... ... ... ... ce # sck io 0 io 1 data out 2 data out 3 mode bits mode bits
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 32 rev. 00b 11/14/2014 figure 8.5 fast read dual i/o sequence (without command decode cycles) notes: 1. if the mode bits=axh ( x: dont care), it can execute the ax read mode (without command). when the mode bits are different from axh (x is dont care), the device exits the ax read operation. 2. number of dummy cycles depends on clock speed. detailed information in table 6.11 read dummy cycles. 3. sufficient dummy cycles are required to avoid i/o contention. if the number of dummy cycles and ax bits cycles are same, then x should be hi- z. 22 ce # sck 2 0 3-byte address 20 18 ... 0 1 2 3 ... 11 12 13 14 15 16 17 18 19 20 21 mode 3 mode 0 23 3 1 21 19 ... io 0 io 1 4 dummy cycles 6 7 6 4 7 5 2 0 3 1 data out t v 6 4 7 5 2 0 3 1 4 5 mode bits ... ... data out
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 33 rev. 00b 11/14/2014 8.5 fast read dual output operation (frdo, 3b h) t he frdo instruction is us ed to read memory da ta on two output pi ns ea ch at up to a 1 33 mhz clock. t he frdo instruction code i s fo ll owed by th ree address bytes (a 23 C a 0) a nd a du mmy by te ( 8 clocks), tr an smitted via the io0 lin e, wi th ea ch bit l at ched-in duri ng t he risi ng edge of sck. t hen the fi rs t data byte a dd re ss ed is shi fted o ut on the io1 and io0 li nes, wi th each pair of bits shifted out at a maximu m frequency fct, duri ng t he fal li ng edge of sck. t he fi rs t bit (msb) is out put on io1. simul ta n eou sly, the second bi t is out put on io0. t he fi rs t byte a dd re ss ed can be at an y memor y locati on. t he address is au tom at ically in cr emented by one after ea ch by te of data i s shifted out. when the hig he st address i s r ea ch ed, the address counter will roll ov er to the 0 00 000h addre ss , allowi ng the en tire memory to be read wi th a single frdo instruction. the frdo instruction is terminated by d ri vi ng ce# hi gh ( vih ). if the frdo instructi on i s i ss ued wh ile an eras e, pr ogr am or write cy cl e is in process (busy=1) the instructi on i s i gno red and w ill not ha ve any ef fec ts on the cu rr ent cy cl e.
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 34 rev. 00b 11/14/2014 fi gure 8.6 f ast read dual output se qu ence ce # sck 7 5 data out 1 instruction = 3bh 23 ce # sck 3 2 1 0 3-byte address high impedance 22 21 ... 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 mode 3 mode 0 48 t v io0 io1 6 4 3 1 7 5 2 0 6 4 3 1 ... 2 0 ... data out 2 io0 io1 8 dummy cycles
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 35 rev. 00b 11/14/2014 8.6 fast read quad output operation (frqo, 6bh) the frqo instruction is used to read memory data on four output pins each at up to a 133 mhz clock. the frqo instruction code is followed by three address bytes (a23 C a0) and a dummy byte (8 clocks), transmitted via the io0 line, with each bit latched-in during the rising edge of sck. then the first data byte addressed is shifted out on the io3, io2, io1 and io0 lines, with each group of four bits shifted out at a maximum frequency fct, during the falling edge of sck. the first bit (msb) is output on io3, while simultaneously the second bit is output on io2, the third bit is output on io1, etc. the first byte addressed can be at any memory location. the address is automatically incremented after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single frqo instruction. frqo instruction is terminated by driving ce# high (vih). if a frqo instruction is issued while an erase, program or write cycle is in process (busy=1) the instruction is ignored and will not have any effects on the current cycle.
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 36 rev. 00b 11/14/2014 figure 8.7 fast read quad output sequence ce # sck 5 1 data out 1 instruction = 6 bh 23 ce # sck 3 2 1 0 3-byte address high impedance 22 21 ... 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 mode 3 mode 0 48 t v io 0 io 1 4 0 5 1 5 1 4 0 4 0 5 1 ... 4 0 ... io 0 io 1 8 dummy cycles high impedance io 2 high impedance io 3 7 3 6 2 7 3 7 3 6 2 6 2 7 3 ... 6 2 ... io 2 io 3 data out 2 data out 3 data out 4
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 37 rev. 00b 11/14/2014 8.7 fast read quad i/o operation (frqio, eb h) the frqio instruction allows the address bits to be input four bits at a time. this may allow for code to be executed directly from the spi in some applications. the frqio instruction code is followed by three address bytes (a23 C a0) and dummy cycles, transmitted via the io3, io2, io1 and io0 lines, with each group of four bits latched-in during the rising edge of sck. the address of msb inputs on io3, the next bit on io2, the next bit on io1, the next bit on io0, and continue to shift in alternating on the four. depending on the usage of ax read operation mode, a mode byte may be located after address input. the first data byte addressed is shifted out on the io3, io2, io1 and io0 lines, with each group of four bits shifted out at a maximum frequency f ct , during the falling edge of sck. the first bit (msb) is output on io3, while simultaneously the second bit is output on io2, the third bit is output on io1, etc. figure 8.8 illustrates the timing sequence. the first byte addressed can be at any memory location. the address is automatically incremented after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single frqio instruction. frqio instruction is terminated by driving ce# high (v ih ). the device supports the ax read operation by applying mode bits during dummy period. mode bits consist of 8 bits, such as m7 to m0. two cycles after address input are reserved for mode bits in frqio execution. m7 to m4 are important for enabling this mode. m3 to m0 become dont care for future use. when m[7:4]=1010(ah), it enables the ax read operation and subsequent frqio execution skips command code. it saves cycles as described in figure 8.9 . when the code is different from axh (x: dont care), the device exits the ax read operation. after finishing the read operation, device becomes ready to receive a new command. spi or qpi mode configuration retains the prior setting. mode bit must be applied during dummy cycles. number of dummy cycles in table 6.11 includes number of mode bit cycles. if dummy cycles are configured as 6 cycles, data output will start right after mode bits and 4 additional dummy cycles are applied. if the frqio instruction is issued while an erase, program or write cycle is in process (wip=1) the instruction is ignored and will not have any effects on the current cycle.
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 38 rev. 00b 11/14/2014 figure 8.8 fast read quad i/o sequence (with command decode cycles) notes: 1. if the mode bits=axh ( x: dont care), it can execute the ax read mode (without command). when the mode bits are different from axh (x is dont care), the device exits the ax read operation . 2. number of dummy cycles depends on clock speed. detailed information in table 6.11 read dummy cycles. 3. sufficient dummy cycles are required to avoid i/o contention. if the number of dummy cycles and ax bits cycles are same, then x should be hi- z. ce # sck 5 1 data out 1 instruction = ebh 20 ce # sck 4 0 4 0 3-byte address high impedance 16 12 8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mode 3 mode 0 32 t v io 0 io 1 4 0 5 1 5 1 4 0 4 0 5 1 4 0 io 0 io 1 21 5 1 5 1 17 13 9 22 6 2 6 2 18 14 10 23 7 3 7 3 19 15 11 mode bits io 2 io 3 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 data out 2 data out 3 data out 4 io 2 io 3 1 0 5 1 ... 4 0 ... 2 6 2 ... 3 7 3 ... 5 4 6 7 6 dummy cycles data out 5 data out 6
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 39 rev. 00b 11/14/2014 figure 8.9 fast read quad i/o sequence (without command decode cycles) notes: 1. if the mode bits=axh ( x: dont care), it can execute the ax read mode (without command). when the mode bits are different from axh (x is dont care), the device exits the ax read operation. 2. number of dummy cycles depends on clock speed. detailed information in table 6.11 read dummy cycles. 3. sufficient dummy cycles are required to avoid i/o contention. if the number of dummy cycles and ax bits cycl es are same, then x should be hi- z. 20 ce # sck 4 0 4 0 3-byte address 16 12 8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 3 mode 0 io 0 io 1 21 5 1 5 1 17 13 9 22 6 2 6 2 18 14 10 23 7 3 7 3 19 15 11 mode bits io 2 io 3 5 1 4 0 5 1 4 0 6 2 6 2 7 3 7 3 ... ... ... ... data out 1 data out 2 16 t v dummy bytes
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 40 rev. 00b 11/14/2014 fast read quad i/o qpi operation ( fr qio qpi, ebh) the frqio qpi instruction is used to read memory data at up to a 1 33 mhz clock. the frqio qpi instruction utilizes all four io lines to input the instruction code so that only two clocks are required, while the frqio instruction requires that the byte-long instruction code is shifted into the device only via io0 line in eight clocks. as a result, 6 command cycles will be reduced by the frqio qpi instruction. in addition, subsequent address and data out are shifted in/out via all four io lines like the frqio instruction. in fact, except for the command cycle, the frqio qpi operation is exactly same as the frqio. a quad enable (qe) bit of status register must be set to "1" before sending the frqio qpi instruction. the device supports the ax read operation by applying mode bits during dummy period. mode bits consist of 8 bits, such as m7 to m0. two cycles after address input are reserved for mode bits in frqio execution. m7 to m4 are important for enabling this mode. m3 to m0 become dont care for future use. when m[7:4]=1010(ah), it enables the ax read operation and subsequent frqio execution skips command code. it saves cycles as described in figure 8.9 . when the code is different from axh (x: dont care), the devic e exits the ax read operation. after finishing the read operation, device becomes ready to receive a new command. spi or qpi mode configuration retains the prior setting. mode bit must be applied during dummy cycles. number of dummy cycles in table 6.11 in cludes number of mode bit cycles. if dummy cycles are configured as 6 cycles, data output will start right after mode bits and 4 additional dummy cycles are applied. if the frqio qpi instruction is issued while an erase, program or write cycle is in proce ss (wip=1) the instruction is ignored and will not have any effects on the current cycle. figure 8. 10 fast read quad i/o sequence , qpi mode note: number of dummy cycles depends on read parameter setting. detailed information in table 6.11 read dummy cycles. e bh ce # sck io [3:0] 6 dummy cycles address 0 1 2 3 4 5 6 7 8 9 ... 13 14 15 16 17 mode 3 mode 0 23 : 20 7:4 3:0 7:4 3:0 data 1 data 2 19 : 16 15 : 12 11 :8 7:4 3:0 18 t v instruction mode bits 7:4 3:0 ...
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 41 rev. 00b 11/14/2014 8.8 pa ge program operation ( pp, 02 h) the page program ( pp ) instruction allows up to 256 bytes data to be programmed into memory in a single operation. the destination of the memory to be programmed must be outside the protected memory area set by the block protection (tbs, bp3, bp2, bp1, bp0) bits. a pp instruction which attempts to program into a page that is write-protected will be ignored. before the execution of pp instruction, the write enable latch (wel) must be enabled through a write enable (wren) instruction. the pp instruction code, three address bytes and program data (1 to 256 bytes) are input via the sl line. program operation will start immediately after the ce# is brought high, otherwise the pp instruction will not be executed. the internal control logic automatically handles the programming voltages and timing. during a program operation, all instructions will be ignored except the rdsr instruction. the progress or completion of the program operation can be determined by reading the wip bit in status register via a rdsr instruction. if the wip bit is 1, the program operation is still in progress. if wip bit is 0, the program operation has completed. if more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the previously latched data are discarded, and the last 256 bytes are kept to be programmed into the page. the starting byte can be anywhere within the page. when the end of the page is reached, the address will wrap around to the beginning of the same page. if the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. note: $surjudprshudwlrqfdqdowhu3vlqwr3vexwdqhudvhrshudwlrqlvuhtxluhgwrfkdqjh3vedfnwr3v a byte cannot be reprogrammed without first erasing the whole sector or block.
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 42 rev. 00b 11/14/2014 figure 8.11 page program sequence figure 8.12 page program sequence (qpi) instruction = 02 h 23 ce # sck si 7 6 so 7 3-byte address high impedance 22 ... 0 data in 1 data in 256 0 1 ... 7 8 9 ... 31 32 33 ... 39 ... 2079 ... 2086 mode 3 mode 0 ... 0 ... ... 0 2087 02 h ce # sck io [3:0] address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 3 mode 0 23 : 20 7:4 3:0 7:4 3:0 data in 1 data in 2 19 : 16 15 : 12 11 :8 7:4 3:0 16 7:4 3:0 7:4 3:0 data in 3 data in 4 ...
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 43 rev. 00b 11/14/2014 8.9 quad input page program operation ( pp q, 32h/ 38h) the quad input page program instruction allows up to 256 bytes data to be programmed into memory in a single operation with four pins (io0, io1, io2 and io3). the destination of the memory to be programmed must be outside the protected memory area set by the block protection (tbs, bp 3, bp2, bp1, bp0) bits. a quad input page program instruction which attempts to program into a page that is write-protected will be ignored. before the execution of quad input page program instruction, the qe bit in the status register must be set to 1 a nd the write enable latch (wel) must be enabled through a write enable (wren) instruction. the quad input page program instruction code, three address bytes and program data (1 to 256 bytes) are input via the four pins (io0, io1, io2 and io3). program operation will start immediately after the ce# is brought high, otherwise the quad input page program instruction will not be executed. the internal control logic automatically handles the programming voltages and timing. during a program operation, all instructions will be ignored except the rdsr instruction. the progress or completion of the program operation can be determined by reading the wip bit in status register via a rdsr instruction. if the wip bit is 1, the program operation is still in progress. if wip bit is 0, the program operation has completed. if more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the previously latched data are discarded, and the last 256 bytes data are kept to be programmed into the page. the starting byte can be anywhere within the page. when the end of the page is reached, the address will wrap around to the beginning of the same page. if the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. note: $surjudprshudwlrqfdqdowhu3vlqwr3vexwdqhudvhrshudwlrqlvuhtxluhgwrfkdqjh3vedfnwr3v a byte cannot be reprogrammed without first erasing the whole sector or block. figure 8 .1 3 quad input page program operation instruction = 32h/38h 23 ce # sck 4 0 4 0 3-byte address high impedance 22 ... 0 0 1 2 3 4 5 6 7 8 9 31 32 33 34 35 mode 3 mode 0 io0 io1 5 1 5 1 6 2 6 2 7 3 7 3 data in 2 io2 io3 ... data in 1 ... ... ... ...
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 44 rev. 00b 11/14/2014 8.10 erase operation the memory array of the is25wp128/064/032 is organized into uniform 4 kbyte sectors or 32k/64 kbyte uniform blocks (a block consists of sixteen adjacent sectors). before a byte is reprogrammed, the sector or block that contains the byte must be erased (erasing sets bits to 1). in order to erase the device, there are three erase instructions available: sector erase ( ser ), block erase (ber) and chip erase (c er). a sector erase operation allows any individual sector to be erased without affecting the data in other sectors. a block erase operation erases any individual block. a chip erase operation erases the whole memory array of a device. a sector erase, block erase, or chip erase operation can be executed prior to any programming operation.
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 45 rev. 00b 11/14/2014 8.11 sector erase operation (ser, d7 h/20h) a sector erase (ser) instruction erases a 4 kbyte sector before the execution of a ser instruction, the write enable latch (wel) must be set via a write enable (wren) instruction. the wel bit is automatically reset after the completion of sector an erase operation. a ser instruction is entered, after ce# is pulled low to select the device and stays low during the entire instruction sequence the ser instruction code, and three address bytes are input via si. erase operation will start immediately after ce# is pulled high. the internal control logic automatically handles the erase voltage and timing. during an erase operation, all instruction will be ignored except the read status register (rdsr) instruction. the progress or completion of the erase operation can be determined by reading the wip bit in the status register using a rdsr instruct ion. if the wip bit is 1, the erase operation is still in progress. if the wip bit is 0, the erase operation has been completed. figure 8.14 sector erase sequence figure 8.15 sector erase sequence (qpi) instruction = d7h/ 20 h 23 ce # sck si 3 2 so 1 0 3-byte address high impedance 22 21 ... 0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31 mode 3 mode 0 d7h/20h ce# sck io[3:0] address 0 1 2 3 4 5 6 7 mode 3 mode 0 23:20 19:16 15:12 11:8 7:4 3:0
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 46 rev. 00b 11/14/2014 8.12 block erase operation (ber32k: 52 h, ber64k: d8 h) a block erase (ber) instruction erases a 32/ 64 kbyte block of the is25wp128/064/032. before the execution of a ber instruction, the write enable latch (wel) must be set via a write enable (wren) instruction. the wel is reset automatically after the completion of a block erase operation. the ber instruction code and three address bytes are input via si. erase operation will start immediately after the ce# is pulled high, otherwise the ber instruction will not be executed. the internal control logic automatically handles the erase voltage and timing. figure 8.16 block erase (64k) sequence figure 8.17 block erase (64k) sequence (qpi) instruction = d8h 23 ce # sck si 3 2 so 1 0 3-byte address high impedance 22 21 ... 0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31 mode 3 mode 0 d8h ce# sck io[3:0] address 0 1 2 3 4 5 6 7 mode 3 mode 0 23:20 19:16 15:12 11:8 7:4 3:0
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 47 rev. 00b 11/14/2014 figure 8.18 block erase sequence (32k) figure 8.19 block erase (32k) sequence (qpi) instruction = 52h 23 ce # sck si 3 2 so 1 0 3-byte address high impedance 22 21 ... 0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31 mode 3 mode 0 52h ce# sck io[3:0] address 0 1 2 3 4 5 6 7 mode 3 mode 0 23:20 19:16 15:12 11:8 7:4 3:0
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 48 rev. 00b 11/14/2014 8.13 chip erase operation (cer, c7 h/60h) a chip erase (c er ) instruction erases the entire memory array of the is25wp128/064/032. before the execution of c er instruction, the write enable latch (wel) must be set via a write enable (wren) instruction. the wel is automatically reset after completion of a chip erase operation. the c er instruction code is input via the si. erase operation will start immediately after ce# is pulled high, otherwise the cer instruction will not be executed. the internal control logic automatically handles the erase voltage and timing. figure 8. 20 chip erase sequence figure 8.21 chip erase sequence (qpi) instruction = c7h/60h ce# sck sio 0 1 2 3 4 5 6 7 mode 3 mode 0 so high impedance c7h/60h ce# sck io[3:0] 0 1 mode 3 mode 0
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 49 rev. 00b 11/14/2014 8.14 write enable operati on (wren, 06h) the write enable (wren) instruction is used to set the write enable latch (wel) bit. the wel bit is reset to the write-protected state after power-up. the wel bit must be write enabled before any write operation, including sector erase , block erase, chip erase, p age program, program information row, write status register , write function register , set non-volatile read register, set non-volatile extended read register, and write autoboot register operations except for set volatile read register and set volatile extended read register. the wel bit will be reset to the write-protect ed state automatically upon completion of a write operation. the wren instruction is required before any above operation is executed. figure 8.22 write enable sequence figure 8.23 write enable sequence (qpi) instruction = 06h ce# sck sio address 0 1 2 3 4 5 6 7 mode 3 mode 0 so high impedance 06h ce# sck io[3:0] 0 1 mode 3 mode 0
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 50 rev. 00b 11/14/2014 8.15 write disable operation (wrdi, 04h) the write disable (wrdi) instruction resets the wel bit and disables all write instructions. the wrdi instruction is not required after the execution of a write instruction, since the wel bit is automatically reset. figure 8.24 write dis able sequence figure 8.25 write dis able sequence (qpi) instruction = 04h ce# sck sio 0 1 2 3 4 5 6 7 mode 3 mode 0 so high impedance 04h ce# sck io[3:0] 0 1 mode 3 mode 0
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 51 rev. 00b 11/14/2014 8.16 read status register operation (rdsr, 05 h) the read status register (rdsr) instruction provides access to the status register. during the execution of a program, erase or write status register operation, all other instructions will be ignored except the rdsr instruction, which can be used to check the progress or completion of an operation by reading the wip bit of status register. figure 8.26 read status register sequence figure 8.27 read status register sequence (qpi) instruction = 05h 7 ce # sck si 3 2 so 1 0 data out 6 5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 3 mode 0 4 t v 05h 0 1 mode 3 mode 0 2 3 7:4 3:0 ce# sck io[3:0] t v data out
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 52 rev. 00b 11/14/2014 8.17 write status register operation (wrsr, 01 h) the write status register (wrsr) instruction allows the user to enable or disable the block protection and status register write protection features by writing 0s or 1s into the non -volatile bp3, bp2, bp1, bp0, qe and srwd bits. figure 8.28 write status register sequence figure 8.29 write status register sequence (qpi) instruction = 01h ce # sck si so data in 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 3 mode 0 7 3 2 1 0 6 5 4 high impedence 01h 0 1 mode 3 mode 0 2 3 7:4 3:0 ce# sck io[3:0] data in
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 53 rev. 00b 11/14/2014 8.18 read function register operation ( rd fr, 48h) the read function register (rdfr) instruction provides access to the erase/program suspend register. during the execution of a program, erase, or write status register suspend , the instruction can be used to check the suspend status. figure 8. 30 read function register sequence figure 8.31 read function register sequence (qpi) instruction = 48h 7 ce # sck si 3 2 so 1 0 data out 6 5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 3 mode 0 4 t v 48h 0 1 mode 3 mode 0 2 3 7:4 3:0 ce# sck io[3:0] t v data out
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 54 rev. 00b 11/14/2014 8.19 write function register operation ( wr f r, 42h) the write function register (wrfr) instruction allows the user to enable or disable additional reset# pin (pin3) on 16-pin soic 300mil package by writing into reset# enable/disable bit, to select top or bottom block area by writing into tbs bit, and lock or unlock the information row by writing 0s (ir lock) or 1s (ir unlock) into irl3, irl2, irl1, irl0. figure 8.32 write function register sequence figure 8.33 write function register sequence (qpi) instruction = 42 h ce # sck si so data in 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 3 mode 0 7 3 2 1 0 6 5 4 high impedence 42 h 0 1 mode 3 mode 0 2 3 7:4 3:0 ce # sck io [3:0] data in
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 55 rev. 00b 11/14/2014 8.20 enter quad peripheral interface (qpi) mode operation (qioen,35h; qiodi,f5h) the enter quad i/o (qio en ) instruction, 35h, enables the flash device for qpi bus operation. upon completion of the instruction, all instructions thereafter will be 4-bit multiplexed input/output until a power cycle or a n exit quad i/o instruction is sent to device. the exit quad i/o instruction, f5h, resets the device to 1-bit spi protocol operation. to execute an exit quad i/o operation, the host drives ce# low, sends the exit quad i/o command cycle, then drives ce# high. the device just accepts sqi (2 clocks) command cycles. figure 8. 34 enter quad peripheral interface (qpi) m ode operation figure 8. 35 exit quad peripheral interface (qpi) m ode o peration instruction = 35h ce # sck si so high impedence 0 1 2 3 4 5 6 7 mode 3 mode 0 f5h ce# sck io[3:0] 0 1 mode 3 mode 0
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 56 rev. 00b 11/14/2014 8.21 program/erase suspend & resume the device allows the interruption of sector erase, block erase, or page program operations to conduct other operations. b0h command for suspend and 30h for resume will be used. (spi/qpi all acceptable) function register bit2 (psus) and bit3 (esus) are used to check wh ether or not the device is in suspend mode. suspend to read ready timing: 10 0s. resume to another suspend timing: 40 0s (recommendation). program/erase suspend during sector-erase or block-erase (persus 75h/b0h) the program/erase suspend allows the interruption of sector erase and block erase operations. after the program/erase suspend, wel bit will be disabled, therefore only read related, resume and reset commands can be accepted. refer to table 8.3 for more detail. to execute the program/erase suspend operation, the host drives ce# low, sends the program/erase suspend command cycle (b0h), then drives ce# high. the function register indicates that the erase has been suspended by changing the esus bit from 0 to 1 , but the device will not accept another command until it is ready. to determine when the device will accept a new command, poll the wip bit in the status register or wait the specified time t su s . when esus bit is issued, the write enable latch (wel) bit will be reset. program/erase suspend during page programming (persus 75h/b0h) program/erase suspend allows the interruption of all program operations. after the program/erase suspend command, wel bit will be disabled, therefore only read related, resume and reset command can be accepted. refer to table 8.3 for more detail. to execute the program/erase suspend operation, the host drives ce# low, sends the program/erase suspend command cycle (b0h), then drives ce# high. the function register indicates that the programming has been suspended by changing the psus bit from 0 to 1 , but the device will not accept another command until it is ready. to determine when the device will accept a new command, poll the wip bit in the status register or wait the specified time t su s . program/erase resume (perrsm 7a/30h) the program/erase resume restarts the program or erase command that was suspended, and changes the suspend status bit in the function register (esus or psus bits) back to 0. to execute the program/erase resume operation, the host drives ce# low, sends the program/erase resume command cycle (30h), then drives ce# high. a cycle is two nibbles long, most significant nibble first. to determine if the internal, self-timed write operation completed, poll the wip bit in the status register, or wait the specified time t se , t be or t pp for sector erase, block erase, or page programming, respectively. the total write time before suspend and after resume will not exceed the uninterrupted write times t se , t be or t pp .
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 57 rev. 00b 11/14/2014 table 8.3 instructions accepted during suspend operation suspended instruction allowed name hex code operation program or erase no rd 03h read data bytes from memory at normal read mode program or erase fr d 0bh read data bytes from memory at fast read mode program or erase frdio bbh fast read dual i/o program or erase frdo 3bh fast read dual output program or erase frqio ebh fast read quad i/o program or erase frqo 6bh fast read quad output program or erase frdtr 0dh fast read dtr mode program or erase frddtr bdh fast read dual i/o dtr program or erase frqdtr edh fast read quad i/o dtr program or erase rdsr 05h read status register program or erase rdfr 48h read function register program or erase perrsm 7ah/30h resume program/erase program or erase rdid abh read manufacturer and product id program or erase srpv c0/63h set read parameters (volatile) program or erase serpv 83h set extended read parameters (volatile) program or erase rdrpnv 61h read read parameters (non - volatile) program or erase rderpnv 81h read extended read parameters (non - volatile) program or erase rdjdid 9fh read manufacturer and product id by jedec id command program or erase rdmdid 90h read manufacturer and device id program or erase rdjdidq afh read jedec id qpi mode program or erase rduid 4bh read unique id number program or erase rdsfdp 5ah sfdp read program or erase nop 00h no operation program or erase rsten 66h software reset enable program or erase rst 99h reset (only along with 66h) program or erase irrd 68h read information row program or erase rdabr e1h read autoboot register
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 58 rev. 00b 11/14/2014 8.22 deep power down (dp, b9 h) the deep power-down (dp) instruction is for setting the device on the minimizing the power consumption (enter into power-down mode). during this mode, standby current is reduced from i sb1 to i sb2 . while in the power-down mode, the device is not active and all write/program/erase instructions are ignored. the instruction is initiated by driving the ce# pin low and shifting the instruction code b9h as s hown in the figure 8 .3 6. the ce# pin must be driven high after the instruction has been latched, or power-down mode will not engage . once ce# pin driven high, the power-down mode will be entered within the time duration of t dp . while in the power-down mode only the release from power-down / rdid instruction, which restores the device to normal operation, will be recognized. all other instructions are ignored, including the read status register instruction which is always available during normal operation. ignoring all but one instruction makes the power down state a useful condition for securing maximum write protection. it is available in both spi and qpi mode. figure 8.36 enter deep p ower down mode o peration (spi) figure 8.37 enter deep p ower down mode o peration (qpi) instruction = b9h ce # sck si ... 0 1 2 3 4 5 6 7 mode 3 mode 0 t dp b9h ce# sck io[3:0] 0 1 mode 3 mode 0 t dp
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 59 rev. 00b 11/14/2014 8.23 release deep power down (rdpd, abh) the release deep power-down/read device id instruction is a multi-purpose command. to release the device from the power-down mode, the instruction is issued by driving the ce# pin low, shifting the instruction code abh and driving ce# high as shown in figure 8.38, 8.39. releasing the device from power-down mode will take the time duration of t res1 before normal operation is re stored and other instructions are accepted. the ce# pin must remain high during the t res1 time duration. if the release deep power-down / rdid instruction is issued while an erase, program or write cycle is in pro gr ess (wip=1) the instruction is ignored and will not have any effects on the current cycle. figure 8.38 release power down sequence (spi) figure 8.39 release power down sequence (qpi) instruction = abh ce # sck si ... 0 1 2 3 4 5 6 7 mode 3 mode 0 t res1 abh ce# sck io[3:0] 0 1 mode 3 mode 0 t res1
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 60 rev. 00b 11/14/2014 8.24 set read parameters operation (srp nv : 65 h, srpv: c0 h/ 63 h) set read parameter bits this device supports configurable burst length and dummy cycles in both spi and qpi mode by setting three bits (p2, p1, p0) and four bits (p6, p5, p4, p3) within the read register, respectively. to set those bits the srpnv and srpv operation instruction are used. details regarding burst length and dummy cycles can be found in table 6.9, table 6.10, and table 6.11. hold#/reset# pin selection (p7) bit in the read register can be set with the srpnv and srpv operation as well, in order to select reset# pin instead of hold# pin. for 16 -pin soic, reset# pin will be a separate pin and it is independent of the p7 bit setting in read register. srpnv is used to set the non-volatile register, while srpv is used to set the volatile register. figure 8. 40 set read parameters operation figure 8.4 1 set read parameters operation (qpi) instruction = 65 h or c0h/ 63 h 7 ce # sck si 3 2 so 1 0 data in 6 5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 3 mode 0 4 high impedance 65 h or c0h/ 63 h 0 1 mode 3 mode 0 2 3 7:4 3:0 ce # sck io [3:0] data in
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 61 rev. 00b 11/14/2014 read with 8/16/32/64 - byte wrap around the device is capable of burst read with wrap around in both spi and qpi mode. the size of burst length is configurable by using p0, p1, and p2 bits in read register. p2 bit (wrap enable) enables the burst mode feature. p0 and p1 define the size of burst. burst lengths of 8, 16, 32, and 64 bytes are supported. by default, address increases by one up through the entire array. by setting the burst length, the data being accessed can be limited to the length of burst boundary within a 256 byte page. the first output will be the data at the initial address which is specified in the instruction. following data will come out from the next address within the burst boundary. once the address reaches the end of boundary, it will automatically move to the first address of the boundary. cs# high will terminate the command. for example, if burst length of 8 and initial address being applied is 0h, following byte output will be from dgguhvvkdqgfrqwlqxhwrkkkk?xqwlo&6whuplqdwhvwkhrshudwlrq,i burst length of 8 and initial address being applied is feh(254d), following byte output will be from address feh and continue to ffh, f8h, f9h, fah, fbh, fch, fdh, and repeat from feh until cs# terminates the operation. 7khfrppdqgv36539kru65319&krukduhxvhgwrfrqiljxuhwkhexuvwohqjwk,iwkhiroorzlqj gdwd lqsxw lv rqh ri 3kkk dqg k wkh ghylfh zloo eh lq ghidxow rshudwlrq prgh ,w zloo eh continuous burst read of the whole array. if the following data input is one ri3kkkdqgkwkh device will set the burst length as 8,16,32 and 64, respectively. 7rh[lwwkhexuvwprghdqrwkhu3&krukfrppdqg is necessary to set p2 to 0. otherwise, the burst mode zloo eh uhwdlqhg xqwlo hlwkhu srzhu grzq ru uhvhw rshudwlrq 7r fkdqjh exuvw ohqjwk dqrwkhu 3&k ru k command should be executed to set p0 and p1 (detail ed information in table 6.9 burst length data). all read commands will operate in burst mode once the read register is set to enable burst mode. refer to figure 8. 40 and figure 8.41 for instruction sequence.
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 62 rev. 00b 11/14/2014 8.25 set extended read parameters operation (s e rp nv : 85h , serpv: 83 h) set read operational driver strength this device supports configurable operational driver strength in both spi and qpi modes by setting three bits (ods0, ods1, ods3) within the extended read register. to set the ods bits the se rp nv and serpv operation instructions are required. the devices driver streng th can be reduced as low as 12.50% of full drive strength. details regarding the driver strength can be found in table 6.14. note: the default driver strength is set to 50% 8.26 read read parameters operation ( rdrp nv , 61 h) prior to, or after setting read register, the data of the read register can be confirmed by the rdrpnv command . the instruction is only applicable for non -volatile read register, not for volatile read register. 8.27 read extended read parameters operation (rdrpnv, 81h) prior to, or after setting extended read register, the data of the extended read register can be confirmed by the rdrpnv command. the instruction is only applicable for non-volatile extended read register, not for volatile extended read register.
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 63 rev. 00b 11/14/2014 8.28 read product identification (rdid, abh) the release from power-down /r ead device id instruction is a multi-purpose instruction. it can support both spi and qpi modes . the read product identification (rdid) instruction is for reading out the old style of 8-bit electronic signature, whose values are shown as table of id definitions. the rdid instruction code is followed by three dummy bytes, each bit being latched-in on si during the rising sck edge . then the device id is shifted out on so with the msb first, each bit been shifted out during the falling edge of sck. the rdid instruction is ended by driving ce# high. the device id ( id 7-id0) outputs repeatedly if additional clock cycles are continuously sent to sck while ce# is at low. table 8.4 product identification manufacturer id (mf7 - mf0) issi serial flash 9dh instruction abh 90h 9fh device density device id (id7 - id0) memory type + capacity (id15 - id0) 128mb 17h 7 018h 64mb 16h 7017h 32mb 15h 7016h figure 8. 42 read product identification sequence instruction = abh device id (id7-id0) ce # sck si device id (id7-id0) so data out 0 1 ... 7 8 9 ... 31 32 33 ... 39 40 41 ... 47 mode 3 mode 0 3 dummy cyles t v
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 64 rev. 00b 11/14/2014 figure 8. 43 read product identification sequence (qpi) abh ce# sck io[3:0] 0 1 mode 3 mode 0 2 3 7:4 3:0 4 5 ... 9 10 11 12 13 6 dummy cyles device id (id7-id0) device id (id7-id0) t v
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 65 rev. 00b 11/14/2014 8.29 read product identification by jedec id operation (rdjdid, 9fh; rdjdidq, afh) the jedec id read instruction allows the user to read the manufacturer and product id of devices. refer to table 8.4 product identification for manufacturer id and device id. after the jedec id read command (9fh in spi mode, afh in qpi mode) is input, the manufacturer id is shifted out msb first followed by the 2-byte electronic id (id15-id0) that indicates memory type and density, one bit at a time. each bit is shifted out during the falling edge of sck. if ce# stays low after the last bit of the 2-byte electronic id, the manufacturer id and 2- byte electronic id will loop until ce# is pulled high. figure 8. 44 read product identification by jedec id read sequence in spi mode figure 8. 45 rd jd idq (read jedec id in qpi mode) operation instruction = 9fh memory type (id15-id8) ce # sck si capacity (id7-id0) so data out 0 1 ... 7 8 9 ... 15 16 17 ... 23 24 25 ... 31 mode 3 mode 0 manufacturer id (mf7-mf0) t v afh ce# sck io[3:0] 0 1 mode 3 mode 0 2 3 7:4 3:0 4 5 7:4 3:0 6 7 7:4 3:0 mf7-mf0 id15-id8 id7-id0 t v
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 66 rev. 00b 11/14/2014 8.30 read device manufacturer and device id operation (rdmdid, 90h) the read product identification (rdid) instruction allows the user to read the manufacturer and product id of devices. refer to table 8.4 product identification for manufacturer id and device id. the rdid instruction code is followed by two dummy bytes and one byte address (a7~a0), each bit being latched-in on si during the rising edge of sck. if one byte address is initially set as a0 = 0, then the manufacturer id (9dh) is shifted out on so with the msb first followed by the device id 7- id0. each bit shifted out during the falling edge of sck. if one byte address is initially set as a0 = 1, then device id 7-id0 will be read first followed by the manufacture id (9dh). the manufacture and device id can be read continuously alternating between the two until ce# is driven high. figure 8. 46 read product identification by rdmdid read sequence notes: 1. address a0 = 0, will output the 1-byte manufacture id (mf7-mf0) ? 1-byte device id (id7-id0) address a0 = 1, will output the 1-byte device id (id7-id0) ? 1-byte manufacture id (mf7-mf0) 2. the manufacture and device id can be read continuously and will alternate from one to the other until ce# pin is pulled high. instruction = 90h manufacturer id (mf7-mf0) ce # sck si device id (id7-id0) so data out 0 1 ... 7 8 9 ... 31 32 33 ... 39 40 41 ... 47 mode 3 mode 0 3 byte address t v
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 67 rev. 00b 11/14/2014 8.31 read unique id number (rduid, 4bh) the read unique id number (rduid) instruction accesses a factory-set read-only 16 -byte number that is unique to the device. the id number can be used in conjunction with user software methods to help prevent copying or cloning of a system. the rduid instruction is instated by driving the ce# pin low and shifting the instruction code (4bh) followed by 3 address bytes and a dummy byte. after which, the 16 -byte id is shifted out on the falling edge of sck as shown below. note: 16 bytes of data will repeat as long as ce# is low and sck is toggling. figure 8.47 rduid operation table 8.5 unique id addressing a[23:16] a[15:9] a[8:4] a[3:0] xxh xxh 00h 0h byte address xxh xxh 00h 1h byte address xxh xxh 00h 2h byte address xxh xxh 00h xxh xxh 00h fh byte address 1rwh;;phdqv3grq?wfduh instruction = 4bh dummy byte ce # sck si so 0 1 ... 7 8 9 ... 31 32 33 ... 39 40 41 ... 47 mode 3 mode 0 3 byte address data out t v
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 68 rev. 00b 11/14/2014 8.32 read sfdp operation (rdsfdp, 5ah) the serial flash discoverable parameter s (sfdp) standard provides a consistent method of describing the functions and features of serial flash devices in a standard set of internal parameter tables. these parameters can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. for more details please refer to the jedec standard jesd216a (serial flash discoverable parameters). the sequence of issuing rdsfdp instruction is same as fast_read: ce# goes low ? send rdsfdp instruction (5ah) ? send 3 address bytes on si pin ? send 1 dummy byte on si pin ? read sfdp code on so ? end rdsfdp operation by driving ce# high at any time during data out. 5hihuwr,66,?v$ssolfdwlrqqrwh for sfdp table. the data at the addresses that are not specified in sfdp table are undefined. figure 8.48 rd sfdp (read sfdp ) operation 8.33 no operation (nop, 00h) the no operation command solely cancels a reset enable command and has no impact on any other commands. it is available in both spi and qpi modes . to execute a nop, the host drives ce# low, sends the nop command cycle (00h), then drives ce# high. instruction = 5ah dummy byte ce # sck si so 0 1 ... 7 8 9 ... 31 32 33 ... 39 40 41 ... 47 mode 3 mode 0 3 byte address data out t v
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 69 rev. 00b 11/14/2014 8.34 software r eset (r eset-enable (rsten, 66h ) and reset (rst, 99h)) and hardware reset the software reset operation is used as a system reset that puts the device in normal operating mode. during the reset operation, the value of volatile registers will default back to the value in the corresponding non-volatile register. this operation consists of two commands: reset-enable (rsten) and reset (rst). the operation requires the reset-enable command followed by the reset command. any command other than the reset command after the reset-enable command will disable the reset-enable. execute the ce# pin low ? sends the reset-enable command (66h), and drives ce# high. next, the host drives ce# low again, sends the reset command (99h), and pulls ce# high. only if the reset# pin is enabled, hardware reset function is available. for all other packages except 16-pin soic 300mil with additional reset# pin option, the reset# pin will be solely applicable in spi mode and when the qe bit is disabled. for 16-pin soic 300mil package with additional reset# pin which is enabled by wkh5(6(7(qdeoh'lvdeohelwvhwwlqj 3 lqglfdwhv(qdeohlq)xqfwlrq5hjlvwhuwkh5(6(7sl n is always applicable regardless of the qe bit value in status register and hold#/reset# selection bit (p7) in read register. the additional reset# pin has an internal pull-up resistor and may be left floating if not used. the reset# pin has the highest priority among all the input signals and will reset the device to its initial power-on state regardless of the state of all other pins (cs, ios, sck, and wp#). in order to activate hardware reset, the reset# pin must be driven low for a minimum period of t reset (1 s). drive reset# low for a minimum period of t reset will interrupt any on-going internal and external operations , release the device from deep power down mode 1 , disable all input signals, force the output pin enter a state of high impedance, and reset all the read parameters. if the reset# pulse is driven for a period shorter than 1s, it may still reset the device, however the 1s minimum period is recommended to ensure the reliable operation. the required wait time after activating a hw reset before the device will accept another instruction (t hwrst ) is the same as the maximum value of t sus (100 s). the software/hardware reset during an active program or erase operation aborts the operation, which can result in corrupting or losing the data of the targeted address range. depending on the prior operation, the reset timing may vary. recovery from a write operation will require more latency than recovery from other operations. note 1: the status and function registers remain unaffected. figure 8.49 software reset enable and software reset operations (rsten, 66h + rst, 99h) instruction = 66h ce# sck sio 0 1 mode 3 mode 0 2 3 4 5 6 7 instruction = 99h 8 9 10 11 12 13 14 15 so high impedance
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 70 rev. 00b 11/14/2014 8.35 security information row the security information row is comprised of an additional 4 x 256 bytes of programmable information. the security bits can be reprogrammed by the user. any program security instruction issued while an erase, program or write cycle is in progress is rejected without having any effect on the cycle that is in progress. table 8.6 information row address address assignment a [23:16] a [15:8] a[7:0] irl0 (information row lock0) 00h 00h byte address irl1 00h 10h byte address irl2 00h 20h byte address irl3 00h 30h byte address bit 7~4 of the function register is used to permanently lock the programmable memory array. when function register bit irlx = 0 , the 256 bytes of the programmable memory array can be programmed. when function register bit irlx = 1 , the 256 bytes of the programmable memory array function as read only.
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 71 rev. 00b 11/14/2014 8.36 information row eras e operation (irer , 64 h) information row erase (irer) instruction erases the data in the information row x (x: 0~3) array. prior to the operation, the write enable latch (wel) must be set via a write enable (wren) instruction. the wel bit is automatically reset after the completion of the operation. the sequence of ir er operation: pull ce# low to select the device ? send irer instruction code ? send three address bytes ? pull ce# high. ce# should remain low during the entire instruction sequence. once ce# is pulled high, erase operation will begin immediately. the internal control logic automatically handles the erase voltage and timing. refer to figure 8. 50 for irer sequence. figure 8. 50 ir er (information row erase ) operation instruction = 64h 23 ce # sck si 3 2 so 1 0 3-byte address high impedance 22 21 ... 0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31 mode 3 mode 0
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 72 rev. 00b 11/14/2014 8.37 information row program operation (irp, 62 h) the information row program ( ir p) instruction allows up to 256 bytes data to be programmed into the memory in a single operation. before the execution of irp instruction, the write enable latch (wel) must be enabled through a write enable (wren) instruction. the irp instruction code, three address bytes and program data (1 to 256 bytes) should be sequentially input. three address bytes has to be input as specified in the section 8.31 security informaion row. program operation will start once the ce# goes high, otherwise the irp instruction will not be executed. the internal control logic automatically handles the programming voltages and timing. during a program operation, all instructions will be ignored except the rdsr instruction. the progress or completion of the program operation can be determined by reading the wip bit in status register via a rdsr instruction. if the wip bit is 1, the program operation is still in progress. if wip bit is 0, the program operation has completed. if more than 256 bytes data are sent to a device, the address counter rolls over within the same page. the previously latched data are discarded and the last 256 bytes data are kept to be programmed into the page. the starting byte can be anywhere within the page. when the end of the page is reached, the address will wrap around to the beginning of the same page. if the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. note: $surjudprshudwlrqfdqdowhu3vlqwr3vexwdqhudvhrshudwlrqlvuhtxluhgwrfkdqjh3vedfnwr3 s. a byte cannot be reprogrammed without first erasing the corresponding information row array which is one of ir0~3. figure 8.51 irp (information row program ) operation instruction = 62h 23 ce # sck si 7 6 so 7 3-byte address high impedance 22 ... 0 data in 1 data in 256 0 1 ... 7 8 9 ... 31 32 33 ... 39 ... 2079 ... 2086 mode 3 mode 0 ... 0 ... ... 0 2087
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 73 rev. 00b 11/14/2014 8.38 information row read operation (irrd, 68 h) the irrd instruction is used to read memory data at up to a 1 33 mhz clock. the irrd instruction code is followed by three address bytes (a23 - a0) and a dummy byte, transmitted via the si line, with each bit latched-in during the rising edge of sck. then the first data byte addressed is shifted out on the so line, with each bit shifted out at a maximum frequency f ct , during the falling edge of sck. the address is automatically incremented after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single irrd instruction. the irrd instruction is terminated by driving ce# high (vih). if a irrd instruction is issued while an erase, program or write cycle is in process (wip=1) the instruction is ignored and will not have any effects on the current cycle figure 8.52 irrd (information row read ) operation instruction = 68h dummy byte ce # sck si so 0 1 ... 7 8 9 ... 31 32 33 ... 39 40 41 ... 47 mode 3 mode 0 3 byte address data out t v
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 74 rev. 00b 11/14/2014 8.39 fast read dtr mode operation (f rdtr, 0dh) the frdtr instruction is for doubling the data in and out . signals are triggered on both rising and falling edge of clock. the address is latched on both rising and falling edge of sck, and data of each bit shifts out on both rising and falling edge of sck at a max imu m frequency f c2 . the 2-bit address can be latched-in at one clock, and 2-bit data can be read out at one clock, which means one bit at the rising edge of clock, the other bit at the falling edge of clock. the first address byte can be at any location. the address is automatically increased to the next higher address after each byte of data is shifted out, so the whole memory can be read out in a single frdtr instruction. the address counter rolls over to 0 when the highest address is reached. the sequence of issuing frdtr instruction is: ce# goes low ? sending frdtr instruction code (1bit per clock) ? 3-byte address on si (2-bit per clock) ? 8 dummy clocks (configurable) on si ? data out on so (2-bit per clock) ? e nd frdtr operation via driving ce# high at any time during data out. (please refer to figure 8.53) while a program/erase/write status register cycle is in progress, frdtr instruction will be rejected without any effect on the current cycle.
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 75 rev. 00b 11/14/2014 figure 8. 53 frdtr (fast read dtr mode ) operation ce # sck si so data out 1 instruction = 0 dh ce # sck si so 3-byte address high impedance 0 1 2 3 4 5 6 7 8 9 10 ... 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 mode 3 mode 0 ... t v 23 22 21 0 7 6 5 4 3 2 1 0 data out 2 7 6 5 4 3 2 1 0 data out ... 7 6 8 dummy cycles 20 19 18 17 ...
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 76 rev. 00b 11/14/2014 fast read dtr qpi mode operation (frdtr qpi, 0dh) the frdtr qpi instruction utilizes all four io lines to input the instruction code so that only two clocks are required, while the frdtr instruction requires that the byte-long instruction code is shifted into the device only via io0 line in eight clocks. in addition, subsequent address and data out are shifted in/out via all four io lines unlike the frdtr instruction. eventually this operation is same as the frqdtr qpi, but the only different thing is that ax mode is not available in the frdtr qpi operation. a quad enable (qe) bit of status register must be set to "1" before sending the frdtr qpi instruction. the sequence of issuing frdtr qpi instruction is: ce# goes low ? sending frdtr qpi instruction (4-bit per clock) ? 24 -bit address interleave on io 3, io 2, io 1 & io 0 (8-bit per clock) ? 6 dummy clocks (configurable) ? data out interleave on io 3, io 2, io 1 & io 0 (8-bit per clock) ? end frdtr qpi operation by driving ce# high at any time during data out. if the frdtr qpi instruction is issued while a program/erase/write status register cycle is in progress (wip=1), the instruction will be rejected without any effect on the current cycle. figure 8. 54 f ast r ead dtr qpi mode operation (f rdtr qpi) notes: 1. number of dummy cycles depends on clock speed. detailed information in table 6.11 read dummy cycles. 2. sufficient dummy cycles are required to avoid i/o contention. if the number of dummy cycles and ax bits cycles are same, then x should be hi- z. instruction = 0 dh ce # sck 3-byte address 0 1 2 3 4 5 6 7 8 9 10 11 12 mode 3 mode 0 t v 20 16 12 5 1 21 17 13 4 0 io 0 io 1 22 18 14 23 19 15 8 4 0 9 5 1 10 6 2 11 7 3 6 dummy cycles io 2 io 3 6 2 7 3 5 1 4 0 6 2 7 3 data out data out 13 4 0 5 1 6 2 7 3 ... ... ... ...
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 77 rev. 00b 11/14/2014 8.40 fast read dual io dtr mode operation (f rddtr, bdh) the frddtr instruction enables double transfer rate throughput on dual i/o of the device in read mode. the ad dress (interleave on dual i/o pins) is latched on both rising and falling edge of sck, and the data (interleave on dual i/o pins) shift out on both rising and falling edge of sck at a maximum frequency f t2 . the 4-bit address can be latched-in at one clock, and 4-bit data can be read out at one clock, which means two bits at the rising edge of clock, the other two bits at the falling edge of clock. the first address byte can be at any location. the address is automatically increased to the next higher address after each byte of data is shifted out, so the whole memory can be read out with a single frddtr instruction. the address counter rolls over to 0 when the highest address is reached. once writing frddtr instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. the sequence of issuing frddtr instruction is: ce# goes low ? sending frddtr instruction (1-bit per clock ) ? 24 -bit address interleave on io 1 & io 0 (4-bit per clock) ? 4 dummy clocks (configurable) on io 1 & io 0 ? data out interleave on io 1 & io 0 (4-bit per clock) ? e nd frddtr operation via pulling ce# high at any time during data out (please refer to figure 8.55 for 2 x i/o double transfer rate read mode timing waveform). ,i$;k;lvgrq?wfduhlvlqsxwiruwkhprghelwvgxulqjgxpp\f\fohvwkhghylfhzloohqwhu ax read operation mode which enables subsequent frdio execution skips command code. it saves cycles as described in figure 8.56 . :khq wkh frgh lv gliihuhqw iurp $;k ; lv grq?w fduh wkh ghylfh h[lwv wkh $; uhdg rshudwlrq $iwhu finishing the read operation, device becomes ready to receive a new command. if the frddtr instruction is issued while a program/erase/write status register cycle is in progress (wip=1) , the instruction will be rejected without any effect on the current cycle.
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 78 rev. 00b 11/14/2014 figure 8.55 frddtr (fast read dual io dtr mode ) operation (with command decode cycles) notes: 1. if the mode bits=axh ( x: dont care), it can execute the ax read mode (without command). when the mode bits are different from axh (x is dont care), the device exits the ax read operation. 2. number of dummy cycles depends on clock speed. detailed information in table 6.11 read dummy cycles. 3. sufficient dummy cycles are required to avoid i/o contention. if the number of dummy cycles and ax bits cycles are same, then x should be hi- z. ce # sck si so instruction = bdh ce # sck si so 3-byte address high impedance 0 1 2 3 4 5 6 7 8 9 10 ... 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 ... mode 3 mode 0 ... t v 22 20 18 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 4 dummy cycles 23 21 19 1 data out ... 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 data out data out data out data out data out ... ... 16 14 12 17 15 13 10 11 7 5 6 4 3 1 2 0 mode bits 30 mode bits
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 79 rev. 00b 11/14/2014 figure 8.56 frddtr (fast read dual io dtr mode ) operation (without command decode cycles) notes: 1. if the mode bits=axh ( x: dont care), it can execute the ax read mode (without command). when the mode bits are different from axh (x is dont care), the device exits the ax read operation. 2. number of dummy cycles depends on clock speed. detailed information in table 6.11 read dummy cycles. 3. sufficient dummy cycles are required to avoid i/o contention. if the number of dummy cycles and ax bits cycles are same, then x should be hi- z. si so 3-byte address ... ... t v 22 20 18 7 5 3 1 7 5 3 1 7 5 3 1 4 dummy cycles 23 21 19 ... 6 4 2 0 6 4 2 0 6 4 2 0 data out data out data out ... ... 16 14 12 17 15 13 10 11 sck 0 1 2 ... 6 7 8 9 10 11 12 13 14 15 16 mode 3 mode 0 ce # 7 5 3 1 6 4 2 0 0 1 mode bits
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 80 rev. 00b 11/14/2014 8.41 fast read quad io dtr mode operation (f rqdtr , ed h) the frqdtr instruction enables double transfer rate throughput on quad i/o of the device in read mode. a quad enable (qe) bit of status register must be set to "1" before sending the frqdtr instruction. the address (interleave on 4 i/o pins) is latched on both rising and falling edge of sck, and data (interleave on 4 i/o pins) shift out on both rising and falling edge of sck at a maximum frequency f q2 . the 8-bit address can be latched-in at one clock, and 8-bit data can be read out at one clock, which means four bits at the rising edge of clock, the other four bits at the falling edge of clock. the first address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out with a single frqdtr instruction. the address counter rolls over to 0 when the highest address is reached. once writing frqdtr instruction, the following address/dummy/data out will perform as 8-bit instead of previous 1-bit. the sequence of issuing frqdtr instruction is: ce# goes low ? sending frqdtr instruction (1-bit per clock) ? 24 -bit address interleave on io 3, io 2, io 1 & io 0 (8-bit per clock) ? 6 dummy clocks (configurable) ? data out interleave on io 3, io 2, io 1 & io 0 (8-bit per clock) ? e nd frqdtr operation by driving ce# hi gh at any time during data out. ,i$;k;lvgrq?wfduhlvlqsxwiruwkhprghelwvgxulqjgxpp\f\fohvwkhghylfhzloohqwhu$;uhdgrshudwlrq mode which enables subsequent frdio execution skips command code. it saves cycles as described in figure 8.58 . :khq wkh frgh lv gliihuhqw iurp $;k ; lv grq?w fduh wkh ghylfh h[lwv wkh $; uhdg rshudwlrq $iwhu finishing the read operation, device becomes ready to receive a new command. if the frqdtr instruction is issued while a program/erase/write status register cycle is in progress (wip=1), the instruction will be rejected without any effect on the current cycle.
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 81 rev. 00b 11/14/2014 figure 8.5 7 frqdtr (fast read quad io dtr mode ) operation (with command decode cycles) notes: 1. if the mode bits=axh ( x: dont care), it can execute the ax read mode (without command). when the mode bits are different from axh (x is dont care), the device exits the ax read operation. 2. number of dummy cycles depends on clock speed. detailed information in table 6.11 read dummy cycles. 3. sufficient dummy cycles are required to avoid i/o contention. if the number of dummy cycles and ax bits cycles are same, then x should be hi- z. ce # sck instruction = edh ce # sck 3-byte address high impedance 0 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 21 22 23 24 25 26 27 mode 3 mode 0 ... t v 20 16 12 5 1 21 17 13 data out ... 4 0 io 0 io 1 io 0 22 18 14 23 19 15 8 4 0 9 5 1 10 6 2 11 7 3 6 dummy cycles io 2 io 3 io 1 io 2 io 3 ... 6 2 ... 7 3 5 1 4 0 6 2 7 3 5 1 4 0 6 2 7 3 5 1 4 0 6 2 7 3 5 1 4 0 6 2 7 3 5 1 4 0 6 2 7 3 5 1 4 0 6 2 7 3 5 1 4 0 6 2 7 3 5 1 4 0 6 2 7 3 5 1 4 0 6 2 7 3 data out data out data out data out data out data out data out data out data out 13 5 1 4 0 6 2 7 3 mode bits
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 82 rev. 00b 11/14/2014 figure 8.58 frqdtr (fast read quad io dtr mode ) operation (without command decode cycles) notes: 1. if the mode bits=axh ( x: dont care), it can execute the ax read mode (without command). when the mode bits are different from axh (x is dont care), the device exits the ax read operation. 2. number of dummy cycles depends on clock speed. detailed information in table 6.11 read dummy cycles. 3. sufficient dummy cycles are required to avoid i/o contention. if the number of dummy cycles and ax bits cycles are same, then x should be hi- z. ce # sck 3-byte address 0 1 2 3 4 5 6 7 8 9 10 11 mode 3 mode 0 ... t v 20 16 12 5 1 21 17 13 ... 4 0 io 0 io 1 22 18 14 23 19 15 8 4 0 9 5 1 10 6 2 11 7 3 6 dummy cycles io 2 io 3 ... 6 2 ... 7 3 5 1 4 0 6 2 7 3 5 1 4 0 6 2 7 3 5 1 4 0 6 2 7 3 data out data out data out data out 5 1 4 0 6 2 7 3 mode bits 12 13
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 83 rev. 00b 11/14/2014 fast read quad io dtr qpi mode operation (frqdtr qpi , edh) the frqdtr qpi instruction utilizes all four io lines to input the instruction code so that only two clocks are required, while the frqdt r instruction requires that the byte-long instruction code is shifted into the device only via io0 line in eight clocks. as a result, 6 command cycles will be reduced by the frqdtr qpi instruction. in addition, subsequent address and data out are shifted in/out via all four io lines like the frqdtr instruction. in fact, except for the command cycle, the frqdtr qpi operation is exactly same as the frqdtr. a quad enable (qe) bit of status register must be set to "1" before sending the frqdtr qpi instruction. the sequence of issuing frqdtr qpi instruction is: ce# goes low ? sending frqdtr qpi instruction (4-bit per clock) ? 24 -bit address interleave on io 3, io 2, io 1 & io 0 (8-bit per clock) ? 6 dummy clocks (configurable) ? da ta out interleave on io 3, io 2, io 1 & io 0 (8-bit per clock) ? end frqdtr qpi operation by driving ce# high at any time during data out. ,i$;k;lvgrq?wfduhlvlqsxwiruwkhprghelwvgxulqjgxpp\f\fohvwkhghylfhzloohqwhu$;uhdgrshudwlrq mode which enables subsequent frdio execution skips command code. it saves cycles as described in figure 8.58 . :khq wkh frgh lv gliihuhqw iurp $;k ; lv grq?w fduh wkh ghylfh h[lwv wkh $; uhdg rshudwlrq $iwhu finishing the read operation, device becomes ready to receive a new command. if the frqdtr qpi instruction is issued while a program/erase/write status register cycle is in progress (wip=1), the instruction will be rejected without any effect on the current cycle. figure 8.59 frqdtr qpi (fast read quad io dtr qpi mode ) operation (with command decode cycles) notes: 1. if the mode bits=axh ( x: grq?w care), it can execute the ax read mode (without command). when the mode bits duhgliihuhqwiurp$;k;lvgrq?wfduhwkhghylfh exits the ax read operation. 2. number of dummy cycles depends on clock speed. detailed information in table 6.11 read dummy cycles. 3. sufficient dummy cycles are required to avoid i/o contention. if the number of dummy cycles and ax bits cycles are same, then x should be hi- z. instruction = edh ce # sck 3-byte address 0 1 2 3 4 5 6 7 8 9 10 11 12 mode 3 mode 0 t v 20 16 12 5 1 21 17 13 4 0 io 0 io 1 22 18 14 23 19 15 8 4 0 9 5 1 10 6 2 11 7 3 6 dummy cycles io 2 io 3 6 2 7 3 5 1 4 0 6 2 7 3 data out data out 5 1 4 0 6 2 7 3 mode bits 13 4 0 5 1 6 2 7 3 ... ... ... ...
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 84 rev. 00b 11/14/2014 8.42 sector lock/unlock functions sector unlock operation (secunlock, 26h) the sector unlock command allows the user to select a specific sector to allow program and erase operations. this instruction is effective when the blocks are designated as write-protected through the bp0, bp1, bp2, and bp3 bits in the status register and tbs bit in function register. only one sector can be enabled at any time. to enable a different sector, a previously enabled sector must be disabled by executing a sector lock command. the instruction code is followed by a 24-bit address specifying the target sector, but a0 through a11 are not decoded. the remaining sectors within the same block remain as read-only. note: in the sector unlock procedure, [a11:a0] must be 0 for the unlock procedure to execute properly. the chip will regard anything else as an illegal command. figure 8. 60 s ecto r unlo ck se qu e n ce notes: 1. if the number of clock cycles do n ot m at ch 8 cycles (command ) + 24 clocks (addre ss) , the command will be ignored. 2. wren (06h) must be executed before sector unlock instructi ons. instruction = 26h ce # sck 3-byte address high impedance 0 1 2 3 4 5 6 7 8 9 10 11 mode 3 mode 0 20 16 12 21 17 13 io0 io1 22 18 14 23 19 15 8 4 0 9 5 1 10 6 2 11 7 3 io2 io3
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 85 rev. 00b 11/14/2014 sector lock operation (seclock, 24h) t he sector lo ck co mm and relocks a sector that was previously unlocked by the sector unlock comman d. t he instructi on code does n ot require an address to be specifi ed , as only one sector can be enabl ed at a tim e. t he remainin g sec to rs wi th in the same block remain in read-onl y m ode. figure 8. 61 sec to r lo ck se qu en ce instruction = 24h ce # sck si so high impedance 0 1 2 3 4 5 6 7 mode 3 mode 0
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 86 rev. 00b 11/14/2014 8.43 autoboot spi devices normally require 32 or more cycles of command and address shifting to initiate a read command. and, in order to read boot code from an spi device, the host memory controller or processor must supply the read command from a hardwired state machine or from some host processor internal rom code. parallel nor devices need only an initial address, supplied in parallel in a single cycle, and initial access time to start reading boot code. the autoboot feature allows the host memory controller to take boot code from the is25wp128/064/032 device immediately after the end of reset, without having to send a read command. this saves 32 or more cycles and simplifies the logic needed to initiate the reading of boot code. ? as part of the power up reset, hardware reset, or command reset process the autoboot feature automatically starts a read access from a pre-specified address. at the time the reset process is completed, the device is ready to deliver code from the starting address. the host memory controller only needs to drive cs# signal from high to low and begin toggling the sck signal. the is25wp128/064/032 device will delay code output for a pre-specified number of clock cycles before code streams out. the auto boot start delay (absd) field of the autoboot register specifies the initial delay if any is needed by the host. the host cannot send commands during this time. if qe bit (bit 6) in the status register is set to 1, quad io read operation will be selected. if it is set to 0, fast read spi operation will be applied. maximum operation frequency will be 133mhz for both operations. ? the starting address of the boot code is selected by the value programmed into the autoboot start address (absa) field of the autoboot register data will continuously shift out until cs# returns high. ? at any point after the first data byte is transferred, when cs# returns high, the spi device will reset to standard spi mode; able to accept normal command operations. a minimum of one byte must be transferred. autoboot mode will not initiate again until another power cycle or a reset occurs. ? an autoboot enable bit (abe) is set to enable the autoboot feature. the autoboot register bits are non-volatile and provide: ? the starting address set by the autoboot start address (absa). ? the number of initial delay cycles, set by the autoboot start delay (absd) 4-bit count value.
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 87 rev. 00b 11/14/2014 figure 8. 62 autoboot sequence (qe = 0) figure 8.63 autoboot sequence (qe = 1) 7 ce # sck si 3 2 so 1 0 data out 1 high impedance 6 5 4 0 1 2 ... n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+ 10 mode 3 mode 0 t v absd delay (n) 7 6 ... data out 2 ... ... 4 ce # sck 4 0 4 0 high impedance 0 4 0 mode 3 mode 0 io 0 io 1 io 2 io 3 5 1 data out 1 5 1 5 1 5 1 7 3 6 2 7 3 7 3 6 2 6 2 7 3 6 2 data out 2 data out 3 data out 4 t v absd delay (n) 0 1 2 ... n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+ 10 ... 4 0 5 1 ... 7 3 ... 6 2 ... data out 5 ... ...
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 88 rev. 00b 11/14/2014 autoboot register read operation (rdabr, e1 h) the autoboot register read command is shifted into si. then the 32 -bit autoboot register is shifted out on so, least significant byte first, most significant bit of each byte first. it is possible to read the autoboot register continuously by providing multiples of 32 clock cycles. figure 8.64 autoboot sequence (qe = 1) instruction = e1h 7 ce # sck si 3 2 so 1 0 data out 1 6 5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 3 mode 0 4 t v ... ...
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 89 rev. 00b 11/14/2014 autoboot register read operation (wrabr, e5h) before the wrabr command can be accepted, a write enable (wren) command must be issued and decoded by the device, which sets the write enable latch (wel) in the status register to enable any write operations. the wr abr command is entered by shifting the instruction and the data bytes on si, least significant byte first, most significant bit of each byte first. the wrabr data is 32 bits in length. cs# must be driven to the logic high state after the 32nd bit of data has been latched. if not, the wrabr command is not executed. as soon as cs# is driven to the logic high state, the self-timed wrabr operation is initiated. while the wrabr operation is in progress, status register 1 may be read to check the value of the write-in progress (wip) bit. the write-in progress (wip) bit is a 1 during the self-timed wrabr op eration, and is a 0 when it is completed. when the wrabr cycle is completed, the write enable latch (wel) is set to a 0. figure 8.65 autoboot sequence (qe = 1) instruction = e5h 7 ce # sck si 3 2 so 1 0 data in 1 6 5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 3 mode 0 4 high impedance ... ...
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 90 rev. 00b 11/14/2014 9. electrical characteristics 9.1 absolute maximum ratings (1) storage temperature - 6 5 c to +1 5 0 c surface mount lead soldering temperature standard package 240 c 3 seconds lead - free package 260 c 3 seconds input voltage with respect to ground on all pins - 0.5v to v cc + 0.5v all output voltage with respect to ground - 0.5v to v cc + 0.5v v cc - 0.5v to + 2.5 v note: 1. applied conditions greater than those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 9.2 operating range part number is25wp128/064/032 operating temperature ( extended grade) - 4 0 c to 1 0 5 c operating temperature (v grade: hybrid flow) - 40c to 125c operating temperature (automotive grade a1) - 40c to 85c operating temperature (automotive grade a2) - 40c to 105c operating temperature (automotive grade a3) - 40c to 125c v cc power supply 1.65v (vmin) 1.95v (vmax) ; 1.8 v (typ)
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 91 rev. 00b 11/14/2014 9.3 dc characteristics (under operating range) symbol parameter condition min typ (2) max units i cc1 v cc active read current (3) nord at 50 mhz, 4 9 ma frd single at 133 mhz 6 8 frd dual at 133 mhz 8 10 frd quad at 133 mhz 10 13 frd quad at 84 mhz 8 10 frd quad at 104 mhz 9 11 frd single ddr at 66 mhz 6 8 frd dual ddr at 66 mhz 8 10 frd quad ddr at 66 mhz 10 13 i cc2 v cc program current ce# = v cc 2 5 3 0 ma i cc3 v cc wrsr current ce# = v cc 25 3 0 i cc4 v cc erase current (4k/32k/64k) ce# = v cc 25 3 0 i cc5 v cc erase current (ce) ce# = v cc 25 3 0 i sb1 v cc standby current cmos ce# = v cc , ce#, reset# ( 4 ) = v cc 8 50 a i sb2 deep power down current ce# = v cc , ce#, reset# ( 4 ) = v cc 1 5 a i li input leakage current v in = 0v to v cc 1 (5 ) a i lo output leakage current v in = 0v to v cc 1 (5 ) a v il (1) input low voltage - 0.5 0. 3 v cc v v ih (1) input high voltage 0.7v cc v cc + 0.3 v v ol output low voltage i ol = 100 a 0. 2 v v oh output high voltage i oh = - 100 a v cc - 0.2 v notes: 1. maximum dc voltage on input or i/o pins is vcc + 0.5v. during voltage transitions, input or i/o pins may overshoot vcc by + 2.0 v for a period of time not to exceed 20ns. minimum dc voltage on input or i/o pins is - 0.5v. during voltage transitions, input or i/o pins may undershoot gnd by -2.0 v for a period of time not to exceed 20ns. 2. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc (typ), ta=25c. 3. outputs are unconnected during reading data so that output switching current is not included. 4. only for the additional reset# pin on 16-pin soic 300mil package. 5. the max of i li and i lo for the additional reset# pin on 16-pin soic 300mil package is 2 a.
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 92 rev. 00b 11/14/2014 9.4 ac measurement conditions symbol parameter min max units cl load capacitance up to 104 mhz 30 pf cl load capacitance up to 133 mhz 15 pf tr,tf input rise and fall times 5 ns vin input pulse voltages 0.2v cc to 0.8v cc v vrefi input timing reference voltages 0.3v cc to 0.7v cc v vrefo output timing reference voltages 0.5v cc v figure 9.1 output test load & ac measurement i/o waveform output pin 1.8k 1.2k 15/30pf 0.8v cc 0.2v cc input v cc /2 ac measurement level
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 93 rev. 00b 11/14/2014 9.5 ac characteristics (under operating range, refer to section 9.4 for ac measurement conditions) symbol parameter min typ (3) max units f ct clock frequency for fast read mode: spi, dual, dual i/o, quad i/o, and qpi. 0 133 mhz f c2 , f t2 , f q2 clock frequency for fast read dtr: spi dtr, dual dtr, dual i/o dtr, quad i/o dtr, and qpi dtr. 0 66 mhz f c clock frequency for read mode spi 0 50 mhz t clch (1) sck rise time (peak to peak) 0.1 v/ns t chcl (1) sck fall time ( peak to peak) 0.1 v/ns t ckh sck high time for read mode 45% f c ns for others 45% f ct/c2/t2/q2 t ckl sck low time for read mode 45% f c ns for others 45% f ct/c2/t2/q2 t ceh ce# high time 7 ns t cs ce# setup time 5 ns t ch ce# hold time 5 ns t ds data in setup time normal mode 2 ns dtr mode 1.5 ns t dh data in hold time normal mode 2 ns dtr mode 1.5 ns t v output valid @ 133mhz (cl = 15pf) 7 ns output valid @ 104mhz (cl = 30pf) 8 ns t oh output hold time normal mode 2 ns t dis (1) output disable time 8 ns t hd output hold time 2 ns t hlch hold active setup time relative to sck 5 ns t chhh hold active hold time relative to sck 5 ns t hhch hold not active setup time relative to sck 5 ns t chhl hold not active hold time relative to sck 5 ns t lz (1) hold to output low z 12 ns t hz (1) hold to output high z 12 ns t ec sector erase time (4kbyte) 45 300 ms block erase time (32kbyte) 0.15 0.75 s block erase time (64kbyte) 0.3 1.5 s chip erase time (32mb) 8 23 s chip erase time (64mb) 16 45 s chip erase time (128mb) 30 90 s t pp page program time 0. 2 1. 0 ms t vc e vcc(min) to ce# low 1 m s
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 94 rev. 00b 11/14/2014 symbol parameter min typ (3) max units t res1 (1) release deep power down 15 s t dp (1) deep power down 3 s t w write status register time 2 15 ms t sus (1) suspend to read ready 100 s t srst (1) software reset recovery time 100 s t reset (1) reset# pin low pulse width 1 (2) s t hwrst (1) hardware reset recovery time 100 s notes: 1. these parameters are characterized and not 100% tested. 2. if the reset# pulse is driven for a period shorter than 1s (t reset minimum), it may still reset the device, however the 1s minimum period is recommended to ensure reliable operation. 3. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc (typ), ta=25c
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 95 rev. 00b 11/14/2014 9.6 serial input/output timing figure 9.2 serial input/output timing (normal mode) (1) note1: for spi mode 0 (0,0) figure 9.3 serial input/output timing (dtr mode) (1) note1: for spi mode 0 (0,0) hi -z so si sck ce # valid in t cs t ckh t ckl t ds t dh t ch t ceh t v t dis hi -z t oh valid in valid output hi -z so si sck ce # valid in t cs t ckh t ckl t ds t dh t ch t ceh t v t dis hi -z t oh valid in valid in output output t v
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 96 rev. 00b 11/14/2014 figure 9. 4 hold timing si so sck ce# hold# t chhl t hlch t chhh t hhch t hz t lz
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 97 rev. 00b 11/14/2014 9.7 power-up and power-down at power-up and power-down, the device must be not selected until vcc reaches at the right level. (adding a simple pull-up resistor on ce# is recommended.) power up timing symbol parameter min. max unit tvce (1) vcc(min) to ce# low 1 m s tpuw (1) power - up time delay to write instruction 1 10 ms v wi (1) write inhibit voltage 1. 3 v note: these parameters are characterized and not 100% tested. v cc v cc (max) v cc (min) v(write inhibit) reset state t vce t puw read access allowed device fully accessible chip selection not allowed all write commands are rejected
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 98 rev. 00b 11/14/2014 9.8 program/erase performance parameter typ max unit sector erase time (4kbyte) 45 3 00 ms block erase time (32kbyte) 0. 1 5 0.75 s block erase time (64kbyte) 0.3 1.5 s chip erase time 32 mb 8 2 3 s 64 mb 16 45 128 mb 30 90 page programming time 0. 2 1. 0 ms byte program 8 40 s note: these parameters are characterized and not 100% tested. 9.9 reliability characteristics parameter min unit test method endurance 1 00,000 cycles jedec standard a117 data retention 20 years jedec standard a103 esd C human body model 2,000 volts jedec standard a114 esd C machine model 200 volts jedec standard a115 latch - up 100 + icc1 ma jedec standard 78 note: these parameters are characterized and not 100% tested.
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 99 rev. 00b 11/14/2014 10. package type information 10.1 8-pin jedec 208mil broad small outline integrated circuit (soic) package (jb) note: all dimensions are in millimeters. 5.38 5.18 5.38 5.18 8.10 7.70 top view 1.27 bsc 0.48 0.35 0.25 0.05 2.16 1.75 side view 0.80 0.50 0.25 0.19 end view 5.33 5.13 5.38 5.18
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 100 rev. 00b 11/14/2014 10.2 8-contact ultra-thin small outline no-lead (wson) package 6x5mm (jk) note: all dimensions are in millimeters. 5.00 bsc 6.00 bsc top view side view 0.25 0.19 0.80 0.70 bottom view pin 1 4.00 3.40 0.48 0.35 1.27 bsc 0.75 0.50
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 101 rev. 00b 11/14/2014 10.3 8-contact ultra-thin small outline no-lead (wson) package 8x6mm (j l) . s y m b o l d i m e n s io n in m m m i n. n o m m a x a 0 . 70 0 . 7 5 0 .80 a 1 0.00 0. 0 2 0.05 a 2 - - - 0 . 2 0 - - - d 7 . 90 8 . 0 0 8 . 10 e 5 . 90 6 . 0 0 6 . 10 d1 4.65 4. 7 0 4.75 e1 4.55 4. 6 0 4.65 e - - - 1 . 2 7 - - - b 0 . 35 0 . 4 0 0 . 48 l 0.4 0. 5 0 0.60 note : all dimensions are in millimeters .
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 102 rev. 00b 11/14/2014 10.4 8-pin 208mil vsop package (jf) symbols min typ max a - - 1 a1 0.05 0.1 0.15 a2 0.75 0.8 0.85 b 0.35 0.42 0.48 c - .127 ref - d 5.18 5.28 5.38 e 7.7 7.9 8.1 e1 5.18 5.28 5.38 e - 1.27 - l 0.5 0.65 0.8 y - - 0.1 0 - 8 note: all dimensions are in millimeters. l e b a a2 a1 c d 10(4x) e1 e
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 103 rev. 00b 11/14/2014 10.5 16 -lead plastic small outline package (300 mils body width) (jm) note: all dimensions are in millimeters. 1.27 0.51 0.33 2.4 2.25 2.35 2.65 0.1 8 0 0 0 1.27 0.4 detail a detail a 0.23 millimeters 1 8 9 16 10.5 10.1 7.4 7.6 10.0 10.65 0.32 0.1 0.3
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 104 rev. 00b 11/14/2014 10.6 24 -ball thin profile fine pitch bga 6x8mm (jg) symbol dimensions (mm) min no m max a - - 1.20 a1 0.27 - 0.37 a2 0.21 ref a3 0.54 ref d 6 bsc e 8 bsc d1 - 3.00 - e1 - 5.00 - e - 1.00 - b - 0.40 - note: all dimensions are in millimeters. (top view) ( bottom view) a1 corner index area a1 corner index area d e 4 3 2 1 a b c d e f e1 e d1 a a3 a2 a1 e nx ?b
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 105 rev. 00b 11/14/2014 11. ordering information- valid part numbers is25wp128 - jb l e temperature range e = extended (- 40 c to +105 c) v = hybrid flow (- 40 c to +125 c) a1 = automotive grade (- 40 c to +85 c) a2 = automotive grade (- 40 c to +105 c) a3 = automotive grade (- 40 c to +125 c) packaging content l = rohs compliant package type ( 1) jb = 8-pin soic 208mil jk = 8-contact wson (6x5mm) jl = 8-contact wson (8x6mm) jf = 8-pin vsop 208mil jm = 16-pin soic 300mil (2) jg = 24 -ball tfbga (6x8mm) jw = kgd (call factory) die revision blank = first revision density 128 = 128 megabit 0 64 = 64 megabit 0 32 = 32 megabit base part number ic = integrated silicon solution inc. 2 5w p = flash, 1.65v ~ 1.95 v, qpi note: 1. call factory for other package options available 2. for the additional reset# pin option, call factory
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 106 rev. 00b 11/14/2014 density frequency (mhz) order part number (1) package 128mb 133 is25wp128 - jble is25wp128 - jblv 8 - pin soic 208mil is25wp128 - jkle is25wp128 - jklv 8 - contact wson (6x5mm) is25wp128 - jlle is25wp128 - jllv 8 - contact wson ( 8x6 mm) is25wp128 - jfle is25wp128 - jflv 8 - pin vsop 208mil is25wp128 - jmle is25wp128 - jmlv 16 - pin soic 300mil (2) is25wp128 - jgle is25wp128 - jglv 24 - ball tfbga (6x8mm) is25wp128 - jbla* 8 - pin soic 208mil (call factory) is25wp128 - jkla* 8 - contact wson (6x5mm) (call factory) is25wp128 - jlla* 8 - contact wson ( 8x6 mm) (call factory) is25wp128 - jfla* 8 - pin vsop 208mil (call factory) is25wp128 - jmla* 16 - pin soic 300mil (2) (call factory) is25wp128 - jgla* 24 - ball tfbga (6x8mm) (call factory) is25wp128 - jwle kgd (call factory) 64mb 133 is25wp064 - jble is25wp064 - jblv 8 - pin soic 208mil is25wp064 - jkle is25wp064 - jklv 8 - contact wson (6x5mm) is25wp064 - jlle is25wp064 - jllv 8 - contact wson (8x6mm) is25wp064 - jfle is25wp064 - jflv 8 - pin vsop 208mil is25wp064 - jmle is25wp064 - jmlv 16 - pin soic 300mil (2) is25wp064 - jgle is25wp064 - jglv 24 - ball tfbga (6x8mm) is25wp064 - jbla* 8 - pin soic 208mil (call factory) is25wp064 - jkla* 8 - contact wson (6x5mm) (call factory) is25wp064 - jlla* 8 - contact wson (8x6mm) (call factory) is25wp064 - jfla* 8 - pin vsop 208mil (call factory) is25wp064 - jmla* 16 - pin soic 300mil (2) (call factory) is25wp064 - jgla* 24 - ball tfbga (6x8mm) (call factory) is25wp064 - jwle kgd (call factory)
is25wp128/064/032 integrated silicon solution, inc.- www.issi.com 107 rev. 00b 11/14/2014 notes: 1. a* = a1, a2, a3: meets aec-q100 requirements with ppap, v = hybrid flow non-auto qualified temp grades: e= -40 to 105 c, v= -40 to 125 c, a1= -40 to 85c, a2= -40 to 105c, a3= -40 to 125c 2. .for the dedicated parts that have additional reset# pin on pin3, call factory density frequency (mhz) order part number (1) package 32mb 133 IS25WP032 - jble IS25WP032 - jblv 8 - pin soic 208mil IS25WP032 - jkle IS25WP032 - jklv 8 - contact wson (6x5mm) IS25WP032 - jlle IS25WP032 - jllv 8 - contact wson (8x6mm) IS25WP032 - jfle IS25WP032 - jflv 8 - pin vsop 208mil IS25WP032 - jmle IS25WP032 - jmlv 16 - pin soic 300mil (2) IS25WP032 - jgle IS25WP032 - jglv 24 - ball tfbga (6x8mm) IS25WP032 - jbla* 8 - pin soic 208mil (call factory) IS25WP032 - jkla* 8 - contact wson (6x5mm) (call factory) IS25WP032 - jlla* 8 - contact wson (8x6mm) (call factory) IS25WP032 - jfla* 8 - pin vsop 208mil (call factory) IS25WP032 - jmla* 16 - pin soic 300mil (2) (call factory) IS25WP032 - jgla* 24 - ball tfbga (6x8mm) (call factory) IS25WP032 - jwle kgd (call factory)

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